MACsec Intel® FPGA IP Release Notes

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ID 722031
Date 7/08/2024
Public
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Document Table of Contents x
1. MACsec Intel® FPGA IP Release Notes
1. MACsec Intel® FPGA IP Release Notes x
1.1. MACsec Intel® FPGA IP v2.5.0 1.2. MACsec Intel® FPGA IP v2.3.0 1.3. MACsec Intel® FPGA IP v2.2.0 1.4. MACsec Intel® FPGA IP v2.1.0 1.5. MACsec Intel® FPGA IP v2.0.0 1.6. MACsec Intel® FPGA IP v1.4.0 1.7. MACsec Intel FPGA IP v1.3.0 1.8. MACsec Intel FPGA IP v1.2.0 1.9. MACsec Intel FPGA IP v1.1.0 1.10. MACsec Intel FPGA IP v1.0.0 1.11. MACsec Intel FPGA IP User Guide Archives
1. MACsec Intel® FPGA IP Release Notes

1.1. MACsec Intel® FPGA IP v2.5.0

Table 1.  v2.5.0 2024.07.08
Quartus® Prime Version Description Impact
24.2

Allowed you to set the replay window to different values on individual ports

The IP performs replay checking successfully even with distinct replay windows set on individual ports.
Fixed the reset polarity for Platform Designer You can now use the IP in a Platform designer connected system correctly. Previously the reset polarity was inverted.

Cleaned the warnings that the IP shows in the message console.

 You see fewer warnings after compiling the example design.
Level Two Title