MACsec Intel® FPGA IP Release Notes

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ID 722031
Date 7/08/2024
Public
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1. MACsec Intel® FPGA IP Release Notes
1. MACsec Intel® FPGA IP Release Notes x
1.1. MACsec Intel® FPGA IP v2.5.0 1.2. MACsec Intel® FPGA IP v2.3.0 1.3. MACsec Intel® FPGA IP v2.2.0 1.4. MACsec Intel® FPGA IP v2.1.0 1.5. MACsec Intel® FPGA IP v2.0.0 1.6. MACsec Intel® FPGA IP v1.4.0 1.7. MACsec Intel FPGA IP v1.3.0 1.8. MACsec Intel FPGA IP v1.2.0 1.9. MACsec Intel FPGA IP v1.1.0 1.10. MACsec Intel FPGA IP v1.0.0 1.11. MACsec Intel FPGA IP User Guide Archives
1. MACsec Intel® FPGA IP Release Notes

1.4. MACsec Intel® FPGA IP v2.1.0

Table 4.  v2.1.0 2023.10.02
Quartus® Prime Version Description Impact
23.3

The ability to change the mux mode has been removed from the GUI and is fixed to be in the STFD mode.

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Rekeying may cause byte counters to report on incorrect secure association (SA) or secure channel (SC). The byte counters might not be accurate per SA or SC. However, the total byte count per physical port will be accurate.

Simulation of the MACsec IP is not supported.

 A patch is required in order to support simulation of the MACsec IP. To obtain this patch, contact Intel Support and reference issue number 14020437750.

Performance is limited. The data source must support backpressure and pause data when the MACsec IP deasserts the TREADY signal on either the TX or RX interfaces.

Failure to pause data when TREADY deasserts can cause undesired side effects.

The performance of the IP is not optimized.

 The exact performance metrics will be documented in the next release.

Single segment mode is not supported. For the 100G configuration, the MACsec IP is therefore only compatible with F-tile.

 The 100G configuration is not supported for E-tile.

The MACsec IP only supports the 1x1 25G, 4x4 25G, and 1X1 100G configurations with 256 bit internal width.

 Other configurations are not supported. In addition, the Example Design generation only supports these configurations.

The GUI option to choose Mux and Demux modes has been removed. The Mux and Demux modules only operate in Store-and-Forward mode.

The IP Upgrade operation updates any cut-through mode settings to Store-and-Forward mode.
Resets can not be asserted simultaneously. Each reset should be enabled in sequence only when the current reset completes. In order to determine when cold_reset completes, wait for cold_reset_ack. For the IP's other resets, asserting the Axi-Lite, Axi-ST, and sw_global resets cause the associated TREADY to deassert and then re-assert. Once you observe this behavior, you can release the reset and continue with either asserting another reset or proceeding to normal operation.
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