MACsec Intel® FPGA IP Release Notes

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ID 722031
Date 7/08/2024
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1. MACsec Intel® FPGA IP Release Notes
1. MACsec Intel® FPGA IP Release Notes x
1.1. MACsec Intel® FPGA IP v2.5.0 1.2. MACsec Intel® FPGA IP v2.3.0 1.3. MACsec Intel® FPGA IP v2.2.0 1.4. MACsec Intel® FPGA IP v2.1.0 1.5. MACsec Intel® FPGA IP v2.0.0 1.6. MACsec Intel® FPGA IP v1.4.0 1.7. MACsec Intel FPGA IP v1.3.0 1.8. MACsec Intel FPGA IP v1.2.0 1.9. MACsec Intel FPGA IP v1.1.0 1.10. MACsec Intel FPGA IP v1.0.0 1.11. MACsec Intel FPGA IP User Guide Archives
1. MACsec Intel® FPGA IP Release Notes

1.5. MACsec Intel® FPGA IP v2.0.0

Table 5.  v2.0.0 2023.06.26
Quartus® Prime Version Description Impact
23.2

Only single 25G (64bit) port with MACsec in 512b data width is supported.

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VLAN and SVLAN packets are not supported. —

When switching SA or SC, you must stop traffic and let the MACsec IP flush out all data before enabling new SA or SC. Once the switch has happened, you can begin sending traffic again.

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If performing a "cold_reset" sequence while data is transiting through the MACsec IP, then a 2nd "cold_reset" sequence is required before starting traffic through the IP again. The "cold_reset" should be asserted once the IP has finished processing the traffic and cleared its buffers.
AXI-ST outputs may have TVALID drops mid-packet, which is incompatible with E-Tile and F-Tile Ethernet IP.

The E- and F-tile Ethernet IPs require continuous transmission with no TVALID drops within a packet. Please request patch for issue 14019703351 to correct this problem.

When mixing the Controlled Port and Uncontrolled Port traffic at the RX Common port, statistics may be incorrectly counted and the Controlled Port packets may be dropped when the parameter "validate_frames" =DISABLED or CHECK. To avoid this issue, set the "validate_frames" parameter to STRICT or NULL.
Only F-tile 1x25G Example Design is supported. The pulldown selections for the Example Design are invalid. The reset sequence for the F-tile 1x25G Example Design is not completely accurate. No Example Designs are available for E-tile.
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