1.3. MACsec Intel® FPGA IP v2.2.0
| Quartus® Prime Version | Description | Impact |
|---|---|---|
| 23.4 | The MACsec IP only supports the 1x1 25G, 4x4 25G, and 1x1 100G configurations with 256 bit internal width. |
Other configurations are not supported. In addition, the Example Design generation only supports these configurations. |
| Performance improved to acheive line rate under most conditions. |
RX line rate performance is supported for sustained non-short length packets. For optimal RX performance, keep payload size above 64 bytes. For the 4x4 configuration, you might not reach line for sustained runs of packets with payload sizes of 65, 97, 129, and 257 bytes. |
|
| All resets are level-sensitive and active-low. Resets are now allowed to be overlapped. |
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| Resets can be asserted simultaneously. |
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