MACsec Intel® FPGA IP Release Notes

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ID 722031
Date 7/08/2024
Public
Document Table of Contents
Document Table of Contents x
1. MACsec Intel® FPGA IP Release Notes
1. MACsec Intel® FPGA IP Release Notes x
1.1. MACsec Intel® FPGA IP v2.5.0 1.2. MACsec Intel® FPGA IP v2.3.0 1.3. MACsec Intel® FPGA IP v2.2.0 1.4. MACsec Intel® FPGA IP v2.1.0 1.5. MACsec Intel® FPGA IP v2.0.0 1.6. MACsec Intel® FPGA IP v1.4.0 1.7. MACsec Intel FPGA IP v1.3.0 1.8. MACsec Intel FPGA IP v1.2.0 1.9. MACsec Intel FPGA IP v1.1.0 1.10. MACsec Intel FPGA IP v1.0.0 1.11. MACsec Intel FPGA IP User Guide Archives
1. MACsec Intel® FPGA IP Release Notes

1.2. MACsec Intel® FPGA IP v2.3.0

Table 2.  v2.3.0 2024.03.31
Quartus® Prime Version Description Impact
24.1

Added Cadence Xcelium support for Example Design simulation.

You can now run Xcelium in the MACsec IP.

Ethernet IP dependency is removed from the MACsec IP Example Design.

The simulation time is faster with the removal of E-Tile or F-Tile Transceivers. There is a wide range of devices available to run the MACsec IP, eliminating the requirement of F-Tile or E-Tile Transceivers in the Example Design.

The MACsec IP GUI for example design generation will show an error if the selected device doesn't support the required Crypto QHIP.

The MACsec IP catches errors earlier during the example design setup, and this supports reducing the setup time impacted by error.

The Replay window must be set to the same value on all ports.

 Failure to set the Replay window to the same value on all ports will result in failure of replay checking, causing either a good packet to be dropped or a bad packet to be received by the user.
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