| 22.3 |
32-bit unaligned addressing is not supported on the MACsec AXI_lite management interface. |
MACsec AXI_lite management supports only 64-bit aligned addresses. |
| Port aliasing issue |
When IP variant contains 1 TX port and 1 RX port, registers corresponding to non-existent ports are enabled. Register read to Port index 2 returns port index 0 values, and port index 3 returns port index 1 values. There are no additional registers generated, but register decoding logic aliases the return values based on index bits. SW/Driver should not read any registers beyond what is targeted in the GUI configuration. |
| Port Mux/Demux registers are not accessible from AXI-lite management bus. |
Register access is unavailable for Mux/Demux blocks. |
| Self-clearing SA is not available. |
When enabling a new SA, user must manually clear old SA. |
| RX maximum crypto channel per port can be more than default value of 8. |
RX maximum crypto channel per port can be selected at IP generation. |
| 200G simplex TX example design for F-tile is now enabled. |
User can generate a 200G simplex TX example design for F-tile. |
| Byte enables is now supported on MACsec AXI-Lite management bus. |
User can now use byte enables on the MACsec AXI-Lite management bus for 64-bit aligned addresses. |
| In simplex configurations, AXI-Lite management bus accesses to the full-duplex register space hangs the AXI-Lite management bus. |
Do not attempt to read an unsupported AXI-Lite register. For example, in a simplex TX configuration, trying to read an RX register hangs the AXI-Lite management bus. |