Symmetric Cryptographic Intel FPGA Hard IP User Guide

ID 714305
Date 10/02/2023
Public
Document Table of Contents

1.5. Resource Utilization

Table 6.  Resource Utilization for Intel® Agilex™ 7 DevicesThese results were obtained using the Intel® Quartus® Prime software version 22.1 with the following conditions:
Device Variant ALM M20K
AGFC023R25A2E2V
  • Enabled all features
  • 0 Ready latency on AXI interfaces
6,855 1 124
  • Generic GCM + XTS
  • Number of MACsec streams = 1
  • Disabled CTS
  • Enabled authentication
  • 0 Ready latency on AXI interfaces
5,1851 53
Table 7.  Theoretical Throughput as a Function of app_ip_st_clk Clock Frequency The following table shows the theoretical throughput which can be achieved with maximum app_ip_st_clk frequencies in different device fabric speed grade.
Fabric Speed Grade app_ip_st_clk Fmax Theoretical Throughput
-1 460Mhz 260Gbps
-2 400Mhz 200Gbps
-3 380Mhz 190Gbps
1 ALM usage can increase up to 10% with higher FPGA utilization. ALM usage also increases if you add ready latency on AXI interfaces.