Symmetric Cryptographic Intel FPGA Hard IP User Guide

ID 714305
Date 10/02/2023
Public
Document Table of Contents

4.6.2. Key RAM ECC Error Handling

The IP core always reports the key RAM ECC error as an internal error, asserting the 0x4 error code.
The cause for this error depends on the specific settings. The below case describes the scenario when you preloaded the tweak value:
  • When you send in a tweak value encrypted with the 2nd key (key 2), the IP returns a tweak value of 0. When the key RAM ECC error code (0x04) asserts and the internal error pin does not assert, the error is due to the encrypted tweak being calculated as a 0.
    Note: When Key RAM ECC error code is masked, this error causes 0x00 error code assertion.
  • A tweak value of 0 weakens the XTS mode. The IP flags this condition as an error. You may choose to ignore this error scenario by masking the 0x04 and 0x00 error codes.