Symmetric Cryptographic Intel FPGA Hard IP User Guide

ID 714305
Date 10/02/2023
Public
Document Table of Contents

2.1. Clock Signals

The app_ip_st_clk clocks almost all soft blocks of the Symmetric Cryptographic Intel FPGA IP core except the reset sequencer logic, which is clocked by app_ip_lite_clk.
Table 8.  Clock SignalsAll clocks are asynchronous to each other.
Port name Width (Bits) Description
i_crypto_clk 1 Clock port for the Symmetric Cryptographic IP core clock.

The clock supports 600 MHz frequency.

app_ip_st_clk 1 Clock source for the AXI-ST interface.

The clock supports

  • 460Mhz frequency in a -1 fabric speed grade
  • 400Mhz frequency in a -2 fabric speed grade
  • 380Mhz frequency in a -3 fabric speed grade
app_ip_lite_clk 1 Clock source for the AXI Lite interface and reset sequencer block.

The clock supports 100 to 150 MHz frequency.