F-Tile Dynamic Reconfiguration Design Example User Guide
ID
710582
Date
8/18/2025
Public
1. Quick Start Guide
2. Detailed Description for CPRI Multirate Design Example
3. Detailed Description for Ethernet Multirate Design Example
4. Detailed Description for Ethernet Multirate Design Example with Auto-Negotiation and Link Training Enabled
5. Detailed Description for PMA/FEC Direct PHY Multirate Design Example
6. Detailed Description for Ethernet to CPRI Design Example
7. Detailed Description for PMA/FEC Direct PHY Static IPs Design Implementation
8. F-Tile Dynamic Reconfiguration Design Example User Guide Archives
9. Document Revision History for the F-Tile Dynamic Reconfiguration Design Example User Guide
3.1.1. Ethernet Multirate Design Example: Simulation Testbench
Figure 9. Simulation Testbench Block Diagram for 25GE-1 Base Variant
Figure 10. Simulation Testbench Block Diagram for 25GE-1 with PTP Base Variant
Figure 11. Simulation Testbench Block Diagram for 100GE-4 Base VariantThe packet client block is available for each of the Ethernet rates.
Figure 12. Simulation Testbench Block Diagram for 100GE-4 with PTP Base VariantThe packet client block is available for each of the Ethernet rates.
Figure 13. Simulation Testbench Block Diagram for 400GE-8 Base VariantThe packet client block is available for each of the Ethernet rates.
Figure 14. Simulation Testbench Block Diagram for 400GE-8 with PTP Base VariantThe packet client block is available for each of the Ethernet rates.
Figure 15. Simulation Testbench Block Diagram for 400G-4 FHT Base Variant
The testbench program controls the testbench components via Avalon® memory-mapped interface access, status and control signals. The Avalon® memory-mapped interface arbiter decodes the Avalon® memory-mapped interface access from testbench program into multiple Avalon® memory-mapped interface slaves.
Simulation Flow:
- Ethernet Multirate IP DUT is power-up based on base profile.
- Initialize the testbench variables based on power-up profile. The parameter settings, located in the basic_avl_tb_top.sv file, are:
- DR_NUM: To indicate the number of dynamic reconfiguration transitions.
- DR_SEQ: To indicate the dynamic reconfiguration sequence.
- Perform dynamic reconfiguration.
- Check the testbench error flag and determine whether testbench passed or failed. The error flag is set to 1 if there is any error after dynamic reconfiguration traffic tests.
For customization, you can modify the DR_NUM and DR_SEQ localparam to configure the test flow. The profile ID is passed to the IP to configure the intended dynamic reconfiguration task.
Dynamic Reconfiguration Sequence Example: 100GE-4 > 2x 50GE-1 > 4x 25GE-1
To achieve this dynamic reconfiguration sequence, you must perform two dynamic reconfiguration transitions and specify the reconfiguration sequence. You update the local parameter settings file:
// Available Modes localparam DR_MODE_1X100GE_4 = 6'b00_00_00; localparam DR_MODE_1X100GE_4_NOFEC = 6'b00_00_01; localparam DR_MODE_1X100GE_2 = 6'b00_00_11; localparam DR_MODE_2x50GE_1 = 6'b01_01_00; localparam DR_MODE_4X25GE_1 = 6'b10_00_00; localparam DR_MODE_4X25GE_1_NOFEC = 6'b10_00_01; // Dynamic Reconfiguration setting localparam DR_NUM = 2; localparam [6:0] DR_SEQ [DR_NUM - 1 : 0] = {DR_MODE_4X25GE_1, DR_MODE_2X50GE_1}