F-Tile Dynamic Reconfiguration Design Example User Guide
ID
710582
Date
8/18/2025
Public
1. Quick Start Guide
2. Detailed Description for CPRI Multirate Design Example
3. Detailed Description for Ethernet Multirate Design Example
4. Detailed Description for Ethernet Multirate Design Example with Auto-Negotiation and Link Training Enabled
5. Detailed Description for PMA/FEC Direct PHY Multirate Design Example
6. Detailed Description for Ethernet to CPRI Design Example
7. Detailed Description for PMA/FEC Direct PHY Static IPs Design Implementation
8. F-Tile Dynamic Reconfiguration Design Example User Guide Archives
9. Document Revision History for the F-Tile Dynamic Reconfiguration Design Example User Guide
4.1.1. AN/LT with Dynamic Reconfiguration Design Example Enhancement: User Logic
To enable real-time execution of the DR flow from within the design, a User Logic block has been added to the Ethernet Multirate Design Examples with AN/LT Enabled. This is a NIOS V-based subsystem that sits at the top level of the example designs. It features a control interface, a clock and reset interface, and an Avalon® memory-mapped interface which connects to the AVMM decoder via an arbiter. Note that the User Logic block is provided for illustrative purposes, and you are free to design your own logic to accomplish the same tasks.