F-Tile Dynamic Reconfiguration Design Example User Guide
ID
710582
Date
8/18/2025
Public
1. Quick Start Guide
2. Detailed Description for CPRI Multirate Design Example
3. Detailed Description for Ethernet Multirate Design Example
4. Detailed Description for Ethernet Multirate Design Example with Auto-Negotiation and Link Training Enabled
5. Detailed Description for PMA/FEC Direct PHY Multirate Design Example
6. Detailed Description for Ethernet to CPRI Design Example
7. Detailed Description for PMA/FEC Direct PHY Static IPs Design Implementation
8. F-Tile Dynamic Reconfiguration Design Example User Guide Archives
9. Document Revision History for the F-Tile Dynamic Reconfiguration Design Example User Guide
1.2.2. Ethernet Multirate Design Example Parameters
Figure 4. Ethernet Multirate Example Design Tab
Parameters | Value | Description |
---|---|---|
Select Protocol/mode | Ethernet |
Select the IP protocol for dynamic reconfiguration. |
Select Base Variant | 25G-1 25G-1 PTP 100G-4 100G-4 PTP 400G-8 400G-8 PTP FHT 400G-4 |
Select the configuration of base variant for dynamic reconfiguration. |
Example Design Files | Simulation Synthesis |
Simulation option generates the testbench and compilation-only project. Synthesis option generates the hardware design example. |
Generated File Format | Verilog VHDL |
Select the HDL files format. If you select VHDL, you must simulate the testbench with a mixed-language simulator. |
Target Development Kit | None Agilex™ 7 I-Series Transceiver-SoC Development Kit DK-SI-AGI027FA Agilex™ 7 I-Series Transceiver-SoC Development Kit DK-SI-AGI027FB |
Target development kit option specifies the target development kit used to generate the project. |
Auto-Negotiation and Link Training Options | ||
Enable auto-negotiation and link training | On Off |
Enables auto-negotiation and link training for the Ethernet port. When the design example is generated using dynamic reconfiguration with AN/LT IP enabled, the design example automatically instantiates the F-Tile Auto-Negotiation and Link Training for Ethernet Intel® FPGA IP. |
Enable auto-negotiation and link training optimized simulation | On Off |
When enabled, reduces the simulation time as much as possible while still maintaining the basic AN/LT protocol and be able to send and receive Ethernet frames. |
Device Initialization Clock | ||
Select Clock | None OSC_CLK_1_25MHZ OSC_CLK_1_100MHZ OSC_CLK_1_125MHZ |
Selects the proper frequency of the OSC_CLK_1 pin on the device in order to match what is provided on the targeted board. |