F-Tile Dynamic Reconfiguration Design Example User Guide

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ID 710582
Date 8/18/2025
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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Detailed Description for CPRI Multirate Design Example 3. Detailed Description for Ethernet Multirate Design Example 4. Detailed Description for Ethernet Multirate Design Example with Auto-Negotiation and Link Training Enabled 5. Detailed Description for PMA/FEC Direct PHY Multirate Design Example 6. Detailed Description for Ethernet to CPRI Design Example 7. Detailed Description for PMA/FEC Direct PHY Static IPs Design Implementation 8. F-Tile Dynamic Reconfiguration Design Example User Guide Archives 9. Document Revision History for the F-Tile Dynamic Reconfiguration Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Compiling the Compilation-Only Project 1.5. Simulating the Design Example Testbench 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Hardware Design Example
1.2. Generating the Design x
1.2.1. CPRI Multirate Design Example Parameters 1.2.2. Ethernet Multirate Design Example Parameters 1.2.3. PMA/FEC Direct PHY Multirate Design Example Parameters 1.2.4. Ethernet to CPRI Design Example Parameters
2. Detailed Description for CPRI Multirate Design Example x
2.1. CPRI Multirate Design Example: Functional Description 2.2. CPRI Multirate Design Example: Registers
2.1. CPRI Multirate Design Example: Functional Description x
2.1.1. CPRI Multirate Design Example: Simulation Testbench 2.1.2. CPRI Multirate Hardware Design Example 2.1.3. CPRI Multirate Design Example: Reset Scheme
3. Detailed Description for Ethernet Multirate Design Example x
3.1. Ethernet Multirate Design Example: Functional Description 3.2. Ethernet Multirate Design Example: Registers
3.1. Ethernet Multirate Design Example: Functional Description x
3.1.1. Ethernet Multirate Design Example: Simulation Testbench 3.1.2. Ethernet Multirate Hardware Design Example 3.1.3. Ethernet Multirate Design Example: Reset Scheme
4. Detailed Description for Ethernet Multirate Design Example with Auto-Negotiation and Link Training Enabled x
4.1. Ethernet Multirate Design Example with AN/LT Enabled: Functional Description
4.1. Ethernet Multirate Design Example with AN/LT Enabled: Functional Description x
4.1.1. AN/LT with Dynamic Reconfiguration Design Example Enhancement: User Logic 4.1.2. Ethernet Multirate Design Example with AN/LT Enabled: Simulation Testbench 4.1.3. Ethernet Multirate Hardware Design Example with AN/LT Enabled
4.1.1. AN/LT with Dynamic Reconfiguration Design Example Enhancement: User Logic x
4.1.1.1. Interfaces 4.1.1.2. Theory of Operation 4.1.1.3. Using Main.cpp file in User Logic 4.1.1.4. User Logic Modes 4.1.1.5. Hardware Testing in Suspend Mode 4.1.1.6. Simulation Testing in Suspend Mode
4.1.3. Ethernet Multirate Hardware Design Example with AN/LT Enabled x
4.1.3.1. Ethernet Multirate Design Example with AN/LT Enabled: Reset Scheme
5. Detailed Description for PMA/FEC Direct PHY Multirate Design Example x
5.1. PMA/FEC Direct PHY Multirate Design Example: Functional Description 5.2. PMA/FEC Direct PHY Multirate Design Example: Registers
5.1. PMA/FEC Direct PHY Multirate Design Example: Functional Description x
5.1.1. PMA/FEC Direct PHY Multirate Design Example: Simulation Testbench 5.1.2. PMA/FEC Direct PHY Multirate Hardware Design Example 5.1.3. PMA/FEC Direct Multirate Design Example: Reset Scheme
6. Detailed Description for Ethernet to CPRI Design Example x
6.1. Ethernet to CPRI Design Example: Functional Description 6.2. Ethernet to CPRI Design Example: Registers
6.1. Ethernet to CPRI Design Example: Functional Description x
6.1.1. Ethernet to CPRI Dynamic Reconfiguration Design Example: Simulation Testbench 6.1.2. Ethernet to CPRI Dynamic Reconfiguration Hardware Design Example 6.1.3. Ethernet to CPRI Dynamic Reconfiguration Design Example: Reset Scheme
1. Quick Start Guide
2. Detailed Description for CPRI Multirate Design Example
3. Detailed Description for Ethernet Multirate Design Example
4. Detailed Description for Ethernet Multirate Design Example with Auto-Negotiation and Link Training Enabled
5. Detailed Description for PMA/FEC Direct PHY Multirate Design Example
6. Detailed Description for Ethernet to CPRI Design Example
7. Detailed Description for PMA/FEC Direct PHY Static IPs Design Implementation
8. F-Tile Dynamic Reconfiguration Design Example User Guide Archives
9. Document Revision History for the F-Tile Dynamic Reconfiguration Design Example User Guide

7. Detailed Description for PMA/FEC Direct PHY Static IPs Design Implementation

This following diagram illustrates the work flow for configuring and implementing DR design using static DPHY profiles:

Follow these steps to configure and implement a DR design using static DPHY profiles,
Figure 44. Configuration and Implementation Workflow for DR Design with Static DPHY Single Channel Profiles
  1. Generate a DR example design by selecting PMA/FEC Direct as the protocol and 50G-1 as the base variant.
  2. After generating the example design, disable the MRIP instantiation (mrip_rcfg_11 dut) in the top module (dphy_f_hw.sv).
  3. Generate the (directphy_f) with the required configuration settings.
  4. Repeat step 3 for each profile needed in the design.
  5. Update the top module by instantiating all generated static IPs and ensuring proper connections for all ports, as illustrated in the examples below.
    Base Profile Instantiation 
    DPHY_Profile_0 DPHY_Profile_0( 
          .rx_cdr_refclk_link(in_refclk_fgt_0_wire_design[0]), 
          .tx_pll_refclk_link(in_refclk_fgt_0_wire_design[0]), 
          .system_pll_clk_link(out_systempll_clk_0_wire), 
          .tx_reset(tx_reset[0]), .rx_reset(rx_reset[0]), 
          .tx_reset_ack(tx_reset_ack), .rx_reset_ack(rx_reset_ack), 
          .tx_ready(tx_ready_dut), .rx_ready(rx_ready_dut), 
          .tx_coreclkin(coreclkin[0]), .rx_coreclkin(coreclkin[0]), 
          .tx_clkout(tx_clkout[0]), .tx_clkout2(tx_clkout2_int[0]),
          .rx_clkout(rx_clkout[0]),
          .rx_clkout2(rx_clkout2_int[0]), 
          .tx_cadence(tx_cadence), 
          .tx_cadence_fast_clk(tx_cadence_fast_clk), 
          .tx_cadence_slow_clk(tx_cadence_slow_clk),
          .tx_serial_data(tx_serial_data[0]), 
          .tx_serial_data_n(tx_serial_data_n[0]),
          .rx_serial_data(rx_serial_data[0]),
          .rx_serial_data_n(rx_serial_data_n[0]), 
          .tx_pll_locked(tx_pll_locked), 
          .rx_is_lockedtodata(rx_is_lockedtodata), 
          .rx_is_lockedtoref(rx_is_lockedtoref),
          .tx_parallel_data(tx_parallel_data), 
          .rx_parallel_data(rx_parallel_data),
          .reconfig_xcvr_clk(i_reconfig_clk), 
          .reconfig_xcvr_reset(reconfig_reset_sync), 
          .reconfig_xcvr_write(reconfig_xcvr_write), 
          .reconfig_xcvr_read(reconfig_xcvr_read), 
          .reconfig_xcvr_address(reconfig_xcvr_address[19:2]), 
          .reconfig_xcvr_byteenable(reconfig_xcvr_byteenable), 
          .reconfig_xcvr_writedata(reconfig_xcvr_writedata),
          .reconfig_xcvr_readdata(reconfig_xcvr_readdata), 
          .reconfig_xcvr_waitrequest(reconfig_xcvr_waitrequest), 
          .reconfig_xcvr_readdatavalid(reconfig_xcvr_readdatavalid), 
          .reconfig_pdp_clk(i_reconfig_clk), .reconfig_pdp_reset(reconfig_reset_sync), 
          .reconfig_pdp_write(reconfig_pdp_write), 
          .reconfig_pdp_read(reconfig_pdp_read), 
          .reconfig_pdp_address(reconfig_pdp_address[16:2]), 
          .reconfig_pdp_byteenable(reconfig_pdp_byteenable), 
          .reconfig_pdp_writedata(reconfig_pdp_writedata), 
          .reconfig_pdp_readdata(reconfig_pdp_readdata),
          .reconfig_pdp_waitrequest(reconfig_pdp_waitrequest),
          .reconfig_pdp_readdatavalid(reconfig_pdp_readdatavalid)
 );
    DPHY_Profile_1 DPHY_Profile_1( 
         .rx_cdr_refclk_link(in_refclk_fgt_2_wire_design[0]), 
         .tx_pll_refclk_link(in_refclk_fgt_2_wire_design[0]),
         .system_pll_clk_link(out_systempll_clk_0_wire),
         .tx_serial_data(tx_serial_data[0]), 
         .tx_serial_data_n(tx_serial_data_n[0]),
         .rx_serial_data(rx_serial_data[0]), 
         .rx_serial_data_n(rx_serial_data_n[0]) ); 
DPHY_Profile_2 DPHY_Profile_2(
         .rx_cdr_refclk_link(in_refclk_fgt_2_wire_design[0]), 
         .tx_pll_refclk_link(in_refclk_fgt_2_wire_design[0]), 
         .system_pll_clk_link(out_systempll_clk_0_wire), 
         .tx_serial_data(tx_serial_data[0]), 
         .tx_serial_data_n(tx_serial_data_n[0]),
         .rx_serial_data(rx_serial_data[0]), 
         .rx_serial_data_n(rx_serial_data_n[0]) 
);
  6. Modify the testbench section in the top module (dphy_f_hw.sv) to incorporate the profiles added to the design.
  7. Assign the pins for any new ports added to the design.
  8. Add the necessary QSF assignments as static profiles are included, using the following format for each assignment. The example below demonstrates the format for two static DPHY profiles.
    • set_instance_assignment -name IP_BB_LOCATION -from <bb_instance_hpath> -to <bb_instance_hpath> -entity <bb-location> 
      set_instance_assignment -name IP_BB_RELATIVE_LOCATION 0 -from 
DPHY_Profile_0|directphy_f_0|dphy_hip_inst|persystem[0].perxcvr[0].fgt.rx_ux.x_bb_f_ux_rx -to
DPHY_Profile_0|directphy_f_0|dphy_hip_inst|persystem[0].perxcvr[0].fgt.rx_ux.x_bb_f_ux_rx -entity dphy_f_hw
 
set_instance_assignment -name IP_BB_RELATIVE_LOCATION 0 -from 
DPHY_Profile_0|directphy_f_0|dphy_hip_inst|persystem[0].perxcvr[0].fgt.tx_ux.x_bb_f_ux_tx -to 
DPHY_Profile_0|directphy_f_0|dphy_hip_inst|persystem[0].perxcvr[0].fgt.tx_ux.x_bb_f_ux_tx -entity dphy_f_hw

set_instance_assignment -name IP_BB_RELATIVE_LOCATION 0 -from 
DPHY_Profile_0|directphy_f_0|dphy_hip_inst|persystem[0].perxcvr[0].fgt.rx_ux.x_bb_f_ux_rx -to 
DPHY_Profile_1|directphy_f_0|dphy_hip_inst|persystem[0].perxcvr[0].fgt.rx_ux.x_bb_f_ux_rx -entity dphy_f_hw
 
set_instance_assignment -name IP_BB_RELATIVE_LOCATION 0 -from 
DPHY_Profile_0|directphy_f_0|dphy_hip_inst|persystem[0].perxcvr[0].fgt.tx_ux.x_bb_f_ux_tx -to 
DPHY_Profile_1|directphy_f_0|dphy_hip_inst|persystem[0].perxcvr[0].fgt.tx_ux.x_bb_f_ux_tx -entity dphy_f_hw 
          
set_instance_assignment -name IP_BB_RELATIVE_LOCATION 0 -from 
DPHY_Profile_0|directphy_f_0|dphy_hip_inst|persystem[0].perehip_rx[0].rx_ehip.x_bb_f_ehip_rx -to 
DPHY_Profile_0|directphy_f_0|dphy_hip_inst|persystem[0].perehip_rx[0].rx_ehip.x_bb_f_ehip_rx -entity dphy_f_hw

set_instance_assignment -name IP_BB_RELATIVE_LOCATION 0 -from 
DPHY_Profile_0|directphy_f_0|dphy_hip_inst|persystem[0].perehip_tx[0].tx_ehip.x_bb_f_ehip_tx -to 
DPHY_Profile_0|directphy_f_0|dphy_hip_inst|persystem[0].perehip_tx[0].tx_ehip.x_bb_f_ehip_tx -entity dphy_f_hw 

set_instance_assignment -name IP_BB_RELATIVE_LOCATION 0 -from 
DPHY_Profile_0|directphy_f_0|dphy_hip_inst|persystem[0].perehip_rx[0].rx_ehip.x_bb_f_ehip_rx -to 
DPHY_Profile_1|directphy_f_0|dphy_hip_inst|persystem[0].perehip_rx[0].rx_ehip.x_bb_f_ehip_rx -entity dphy_f_hw

set_instance_assignment -name IP_BB_RELATIVE_LOCATION 0 -from 
DPHY_Profile_0|directphy_f_0|dphy_hip_inst|persystem[0].perehip_tx[0].tx_ehip.x_bb_f_ehip_tx -to 
DPHY_Profile_1|directphy_f_0|dphy_hip_inst|persystem[0].perehip_tx[0].tx_ehip.x_bb_f_ehip_tx -entity dphy_f_hw
      Note: You do not need to perform this QSF assignment if you assign the relative serial port PIN location, which allows you to bypass the BB LOCATION assignment.
    • set_instance_assignment -name IP_RECONFIG_ID -to <ip_instance_hpath> <positive-number-greater-than-zero> 
      Example:
set_instance_assignment -name IP_RECONFIG_ID 1 -to DPHY_Profile_0|directphy_f_0 -entity dphy_f_hw 
set_instance_assignment -name IP_RECONFIG_ID 2 -to DPHY_Profile_1|directphy_f_0 -entity dphy_f_hw
    • set_global_assignment -name IP_RECONFIG_GROUP_TYPE <reconfig-group-id-string>:<exclusive|inclusive>:clk_master 
      Example:
set_global_assignment -name IP_RECONFIG_GROUP_TYPE "RG_A:EXCLUSIVE:SHARED_SIP:CLK_MASTER"
    • set_instance_assignment -name IP_RECONFIG_GROUP -to <ip_instance_hpath> <reconfig-group-id-string> 
      Example:
set_instance_assignment -name IP_RECONFIG_GROUP RG_A -to DPHY_Profile_0|directphy_f_0 -entity dphy_f_hw 
set_instance_assignment -name IP_RECONFIG_GROUP RG_A -to DPHY_Profile_1|directphy_f_0 -entity dphy_f_hw
    • set_instance_assignment -name IP_RECONFIG_GROUP_STARTUP_INSTANCE ON|OFF -to <ip_instance_hpath> 
      Example:
set_instance_assignment -name IP_RECONFIG_GROUP_STARTUP_INSTANCE ON -to DPHY_Profile_0|directphy_f_0 -entity dphy_f_hw
    • set_instance_assignment -name IP_COLOCATE -from <hpath1> -to <hpath2> F_TILE 
      Example:
set_instance_assignment -name IP_COLOCATE F_TILE -from dr_dut|dr_f_0 -to DPHY_Profile_0|directphy_f_0 -entity dphy_f_hw 
set_instance_assignment -name IP_COLOCATE F_TILE -from dr_dut|dr_f_0 -to DPHY_Profile_1|directphy_f_0 -entity dphy_f_hw
    • set_instance_assignment -name IP_RECONFIG_GROUP_MASTER_CLOCK_CHANNEL -to <bb_instance_hpath> <clock-port-name> 
      Example:
set_instance_assignment -name IP_RECONFIG_GROUP_MASTER_CLOCK_CHANNEL PLD_PCS_TX_CLK_OUT1_DCM -to 
DPHY_Profile_0|directphy_f_0|dphy_hip_inst|persystem[0].perxcvr[0].peraib[0].tx_aib.x_bb_m_hdpldadapt_tx -entity dphy_f_hw
    • set_instance_assignment -name IP_RECONFIG_GROUP_SHARED_SIP -to <to> -entity <entity name> <value> 
      Example:
set_instance_assignment -name IP_RECONFIG_GROUP_SHARED_SIP ON -to DPHY_Profile_0|directphy_f_0 -entity dphy_f_hw
    Note: Find the path information for bb_instance_hpath or ip_instance_hpath of each profile in …/hardware_test_design/support_logic/dphy_f_hw_tile_placement.json.
  9. In hardware test scripts, modify the following:
    • Change the following to base profile configuration in …/hwtest/tests/ftile_dphy_dr_test.tcl.
      set current_dr_profile $PROFILE_ID_50G 
set_dr_mode $DR_MODE_50G 0 $fileid 
set variant_name "1x50G"
    • Update the highlighted expression value in each process of the rates as per the profile order generated in the design, and make the changes in the file …/hwtest/src/dr_seq.tcl.
      # Step 2: Triggering Reconfiguration 
          puts "\tINFO: configuring DR Profile $desire_id_name...." 
          write_dr_ctrl_mc_cfgcsr_reg $ch $::dyn_rcfg_dr_next_profile_0_reg [expr 0x00000000 | $current_id] 
          write_dr_ctrl_mc_cfgcsr_reg $ch $::dyn_rcfg_dr_next_profile_1_reg [expr 0x00008001]

      Refer to the section below for detailed guidance on assigning the value, as described in the Dynamic Reconfiguration Control and Status Register (dyn_rcfg_dr_next_profile_1_reg).

    • Change the highlighted information and order of profiles as configured in the design in …/hwtest/src/parameter.tcl.
      set power_up_variant 1x50G 
set loopback_mode 0 set DR_TRANSITION(0) "1x25G" 
set DR_TRANSITION(1) "1x50G KPFEC"
set DR_TRANSITION(2) "1x24.33024G" 
set DR_TRANSITION(3) "1x10.1376G" 
set DR_TRANSITION(4) "1x9.8304G" 
set DR_TRANSITION(5) "1x4.9152G" 
set DR_TRANSITION(6) "1x2.4576G" 
set DR_TRANSITION(7) "1x10G" 
set DR_TRANSITION(8) "1x50G"
set PROFILE_ID_50G 1 set PROFILE_ID_50GKP 2 
set PROFILE_ID_25G 3 set PROFILE_ID_24G 4 
set PROFILE_ID_10P1G 5 set PROFILE_ID_9P8G 6 
set PROFILE_ID_4P9G 7 set PROFILE_ID_2P4G 8 
set PROFILE_ID_10G 9
set DR_MODE_50G 0
set DR_MODE_25G 1 
set DR_MODE_24G 2 
set DR_MODE_10P1G 3 
set DR_MODE_9P8G 4 
set DR_MODE_4P9G 5 
set DR_MODE_2P4G 6 
set DR_MODE_10G 7 
set DR_MODE_50GKP 8
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