F-Tile Dynamic Reconfiguration Design Example User Guide

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ID 710582
Date 8/18/2025
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Detailed Description for CPRI Multirate Design Example 3. Detailed Description for Ethernet Multirate Design Example 4. Detailed Description for Ethernet Multirate Design Example with Auto-Negotiation and Link Training Enabled 5. Detailed Description for PMA/FEC Direct PHY Multirate Design Example 6. Detailed Description for Ethernet to CPRI Design Example 7. Detailed Description for PMA/FEC Direct PHY Static IPs Design Implementation 8. F-Tile Dynamic Reconfiguration Design Example User Guide Archives 9. Document Revision History for the F-Tile Dynamic Reconfiguration Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Compiling the Compilation-Only Project 1.5. Simulating the Design Example Testbench 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Hardware Design Example
1.2. Generating the Design x
1.2.1. CPRI Multirate Design Example Parameters 1.2.2. Ethernet Multirate Design Example Parameters 1.2.3. PMA/FEC Direct PHY Multirate Design Example Parameters 1.2.4. Ethernet to CPRI Design Example Parameters
2. Detailed Description for CPRI Multirate Design Example x
2.1. CPRI Multirate Design Example: Functional Description 2.2. CPRI Multirate Design Example: Registers
2.1. CPRI Multirate Design Example: Functional Description x
2.1.1. CPRI Multirate Design Example: Simulation Testbench 2.1.2. CPRI Multirate Hardware Design Example 2.1.3. CPRI Multirate Design Example: Reset Scheme
3. Detailed Description for Ethernet Multirate Design Example x
3.1. Ethernet Multirate Design Example: Functional Description 3.2. Ethernet Multirate Design Example: Registers
3.1. Ethernet Multirate Design Example: Functional Description x
3.1.1. Ethernet Multirate Design Example: Simulation Testbench 3.1.2. Ethernet Multirate Hardware Design Example 3.1.3. Ethernet Multirate Design Example: Reset Scheme
4. Detailed Description for Ethernet Multirate Design Example with Auto-Negotiation and Link Training Enabled x
4.1. Ethernet Multirate Design Example with AN/LT Enabled: Functional Description
4.1. Ethernet Multirate Design Example with AN/LT Enabled: Functional Description x
4.1.1. AN/LT with Dynamic Reconfiguration Design Example Enhancement: User Logic 4.1.2. Ethernet Multirate Design Example with AN/LT Enabled: Simulation Testbench 4.1.3. Ethernet Multirate Hardware Design Example with AN/LT Enabled
4.1.1. AN/LT with Dynamic Reconfiguration Design Example Enhancement: User Logic x
4.1.1.1. Interfaces 4.1.1.2. Theory of Operation 4.1.1.3. Using Main.cpp file in User Logic 4.1.1.4. User Logic Modes 4.1.1.5. Hardware Testing in Suspend Mode 4.1.1.6. Simulation Testing in Suspend Mode
4.1.3. Ethernet Multirate Hardware Design Example with AN/LT Enabled x
4.1.3.1. Ethernet Multirate Design Example with AN/LT Enabled: Reset Scheme
5. Detailed Description for PMA/FEC Direct PHY Multirate Design Example x
5.1. PMA/FEC Direct PHY Multirate Design Example: Functional Description 5.2. PMA/FEC Direct PHY Multirate Design Example: Registers
5.1. PMA/FEC Direct PHY Multirate Design Example: Functional Description x
5.1.1. PMA/FEC Direct PHY Multirate Design Example: Simulation Testbench 5.1.2. PMA/FEC Direct PHY Multirate Hardware Design Example 5.1.3. PMA/FEC Direct Multirate Design Example: Reset Scheme
6. Detailed Description for Ethernet to CPRI Design Example x
6.1. Ethernet to CPRI Design Example: Functional Description 6.2. Ethernet to CPRI Design Example: Registers
6.1. Ethernet to CPRI Design Example: Functional Description x
6.1.1. Ethernet to CPRI Dynamic Reconfiguration Design Example: Simulation Testbench 6.1.2. Ethernet to CPRI Dynamic Reconfiguration Hardware Design Example 6.1.3. Ethernet to CPRI Dynamic Reconfiguration Design Example: Reset Scheme
1. Quick Start Guide
2. Detailed Description for CPRI Multirate Design Example
3. Detailed Description for Ethernet Multirate Design Example
4. Detailed Description for Ethernet Multirate Design Example with Auto-Negotiation and Link Training Enabled
5. Detailed Description for PMA/FEC Direct PHY Multirate Design Example
6. Detailed Description for Ethernet to CPRI Design Example
7. Detailed Description for PMA/FEC Direct PHY Static IPs Design Implementation
8. F-Tile Dynamic Reconfiguration Design Example User Guide Archives
9. Document Revision History for the F-Tile Dynamic Reconfiguration Design Example User Guide

9. Document Revision History for the F-Tile Dynamic Reconfiguration Design Example User Guide

Document Version Quartus® Prime Version Changes
2025.08.011 24.3 Added new chapter: Detailed Description for PMA/FEC Direct PHY Static IPs Design Implementation.
2024.11.04 24.3 Made the following changes:
  • Updated the design example GUI to show Select Clock parameter in the following sections:
    • CPRI Multirate design example parameters
    • Ethernet Multirate Design Example Parameters
    • PMA/FEC Direct PHY Multirate Design Example Parameters
  • Added Select Clock parameter in the following sections to support different board and development kit clock frequencies:
    • CPRI Multirate design example parameters
    • Ethernet Multirate Design Example Parameters
    • PMA/FEC Direct PHY Multirate Design Example Parameters
  • Added new chapter: ANLT + DR ED Enhancement: User Logic along with the following subsections:
    • Interfaces and tables
    • Theory of Operation
    • Using Main.cpp file in User Logic
    • User Logic Modes
    • Hardware Testing in Suspend Mode
    • Simulation Testing in Suspend Mode
  • Updated the Images in the Ethernet Multirate Design Example with AN/LT Enabled: Simulation to show User Logic block between F-Tile Auto-Negotiation and Link Training for Ethernet Intel® FPGA IP IP and Avalon® Memory-Mapped Arbiter.
  • Updated the images to show User Logic block in the Ethernet Multirate Hardware Design Example with AN/LT Enabled section.
2024.04.11 24.1 Made the following changes:
  • Corrected the table 8 title in Simulating the Design Example Testbench.
  • Updated Ethernet Multirate Example Design Tab image in Ethernet Multirate Design Example Parameters.
  • Added new parameter: Enable Auto-Negotiation and Link Training optimized simulation under Auto-Negotiation and Link Training Options tab in Ethernet Multirate Design Example Parameters.
  • Added a new block diagram Ethernet to CPRI Dynamic Reconfiguration Hardware Design Example Block Diagram (25G-1 PTP with RS-FEC (with 1G PTP) in Ethernet to CPRI Dynamic Reconfiguration Hardware Design Example.
2023.10.06 23.3 Made the following changes:
  • For generated design examples, updated the choice of the targeted development kits to:
    • Agilex™ 7 I-series Transceiver-SoC Development Kit DK-SI-AGI027FA
    • Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit DK-SI-AGI027FB
  • Added new parameter: Enable auto-negotiation and Link Training in Ethernet Multirate Design Example Parameters.
  • Added new paragraph about dynamic reconfiguration transition process in Testing the Hardware Design Example.
  • Added new topic: Ethernet Multirate Design Example: Reset Scheme in Detailed Description of Ethernet Multirate Design Example.
  • Added a new chapter: Detailed Description for Ethernet Multirate Design Example with AN/LT Enabled.
  • Added new topic: Ethernet Multirate Design Example with AN/LT Enabled: Reset Scheme.
  • Added new topic: PMA/FEC Direct Multirate Design Example: Reset Scheme in Detailed Description of PMA/FEC Direct Multirate Design Example.
  • Added new base variant for the Ethernet to CPRI Protocol Design Example in Ethernet to CPRI Design Example: Functional Description.
    • 25G-1 PTP with RS-FEC (with 1GE PTP)
  • Added Simulation Testbench Block Diagram for Ethernet to CPRI Dynamic Reconfiguration Design Example (With 1GE PTP) diagram in Ethernet to CPRI Dynamic Reconfiguration Design Example: Simulation testbench.
  • Added a new topic: Ethernet to CPRI Dynamic Reconfiguration Design Example: Reset Scheme in Detailed Description for Ethernet to CPRI Design Example.
  • Updated the target device list for Target Development Kit parameter in the following sections:
    • CPRI Multirate Design Example Parameters
    • Ethernet Multirate Design Example Parameters
    • PMA/FEC Direct PHY Multirate Design Example Parameters
    • Ethernet to CPRI Design Example Parameters
2023.08.17 23.2 Corrected the signal direction for TX and RX serial ports for the following images:
  • Simulation Testbench Block Diagram for Ethernet to CPRI Dynamic Reconfiguration Design Example.
  • Simulation Testbench Block Diagram for Ethernet to CPRI Dynamic Reconfiguration Design Example (with 1GE) in Ethernet to CPRI Dynamic Reconfiguration Design Example: Simulation Testbench.
  • Ethernet to CPRI Dynamic Reconfiguration Hardware Design Example Block in Ethernet to CPRI Dynamic Reconfiguration Hardware Design Example.
2023.04.03 23.1
  • Added new base variant for the Ethernet to CPRI Protocol in section: Quick Start Guide.
    • 25G-1 with RS-FEC with 1GE
  • Updated Ethernet to CPRI Example Design Tab image in Ethernet to CPRI Design Example Parameters.
  • Added Example Design Files parameter value: Synthesis in Ethernet to CPRI Design Example Parameters.
  • Added new base variant for the Ethernet to CPRI Protocol in section: Ethernet to CPRI Design Example: Functional Description.
  • Added new image Simulation Testbench Block Diagram for Ethernet to CPRI Dynamic Reconfiguration Design Example (with 1GE).
  • Added Address Map for Ethernet to CPRI Variant (with 1GE) in Ethernet to CPRI Design Example: Registers.
  • Updated the product family name to "Intel Agilex 7."
2022.12.19 22.4 Added the following:
  • Hardware Design Example File Descriptions for Ethernet to CPRI Multirate Designs in Directory Structure.
  • Step 4 note in Testing the Hardware Design Example.
  • Ethernet Multirate Hardware Design Example Block Diagram for 400GE-4 FHT Base Variant in Ethernet Multirate Hardware Design Example.
  • Address Map for 400GE-4 FHT Base Variant in Ethernet Multirate Design Example: Registers.
  • PMA/FEC Direct PHY Multirate Hardware Design Example Block Diagram: 400G-8 Base Variant in PMA/FEC Direct PHY Multirate Hardware Design Example.
  • Updated Ethernet to CPRI simulation testbench block diagram in Ethernet to CPRI Dynamic Reconfiguration Design Example: Simulation Testbench
  • Added Ethernet to CPRI Dynamic Reconfiguration Hardware Design Example.
  • Added address map for Ethernet to CPRI variant in Ethernet to CPRI Design Example: Registers.
2022.09.26 22.3
  • Added new Ethernet base variant in section: Quick Start Guide.
    • FHT 400G-4 with RS-FEC
  • Added new base variants for the Ethernet to CPRI Protocol in section: Quick Start Guide.
    • 25G-1 RS-FEC
  • Added FHT 400G-4 base variant for Ethernet IP protocol.
  • Updated hardware flow design example steps in Ethernet Multirate Hardware Design Example.
  • Added simulation testbench block diagram for 400G-4 FHT Base variant in Ethernet Multirate Design Example: Simulation Testbench.
  • Added multirate hardware design example block diagram for the following PTP Base Variants:
    • 25GE-1 with PTP
    • 100GE-4 with PTP
    • 400GE-8 with PTP
  • Added new topic: Ethernet to CPRI Design Example Parameters in Generating the Design section.
  • Added Key Testbench and Simulation Files for Ethernet to CPRI Multirate Designs in Directory Structure section.
  • Added simulation test run results for the Ethernet to CPRI design example testbench in section Simulating the Design Example Testbench.
  • Updated the PMA/FEC Direct PHY Multirate Hardware Design Example section with steps for the hardware flow.
  • Updated the PMA/FEC Direct PHY Multirate Design Example: Registers section with address map for 400G-8 base variant.
  • Added new section: Detailed Description for Ethernet to CPRI Protocol Dynamic Reconfiguration Design Example.
2022.06.21 22.2
  • Updated the Supported Configuration table in section: Quick Start Guide:
    • Added new base variants for the Ethernet and PMA/FEC Direct PHY IP protocol.
      • Ethernet base variants:
        • 100G-4 with RS-FEC and PTP
        • 25G-1 with RS-FEC and PTP
        • 400G-8 with RS-FEC and PTP
      • PMA/FEC Direct PHY base variant: 400G-8 with RS-FEC
    • Added corresponding new information in section: Detailed Description for Ethernet Multirate Design Example and Detailed Description for PMA/FEC Direct PHY Multirate Design Example.
  • Updated the Select Base Variant parameter in section: Ethernet Multirate Design Example Parameters.
  • Updated the following PMA/FEC Direct PHY Multirate Design Example Parameters:
    • Select Base Variant
    • Generated File Format
    • Target Development Kit
  • Added hardware support for 400G-8 base variant of the Ethernet Multirate Designs.
  • Added hardware support for 50G-1 base variant of the PMA/FEC Direct PHY Multirate Designs.
    • Added new section: PMA/FEC Direct PHY Multirate Hardware Design Example.
  • Updated the Ethernet Multirate Design Example: Registers section with 400G-8 base variant address map.
2022.03.28 22.1
  • Updated the Supported Configuration table in Quick Start Guide:
    • Added new target variants for the Ethernet 100GE-1 base variant
    • Added 400GE-8 base variant for Ethernet IP protocol
    • Added 50G-1 base variant for PMA/FEC direct IP protocol
  • Removed support for the ModelSim* SE simulator.
  • Updated Ethernet Multirate Design Example Parameters to include 400G-8 base variant and the dev kit support.
  • Updated steps in section: Simulating the Design Example Testbench.
  • Updated Directory Structure:
    • Added PMA/FEC Direct PHY-specific testbench files
    • Added Ethernet-specific hardware design example files
  • Added new figure: Simulation Testbench Block Diagram for 400GE-8 Base Variant
  • Added hardware support for the Ethernet Multirate Design Example.
  • Added support for PMA/FEC Direct PHY Multirate design example.
2022.01.07 21.4
  • Added support for Ethernet Multirate design example.
  • Added support for the Xcelium* simulator.
  • Added hardware support for the CPRI Multirate Design Example.
  • Updated the Simulation Testbench Block Diagram and the customization instructions in section: CPRI Multirate Design Example: Simulation Testbench.
  • Updated the address range in section: CPRI Multirate Design Example: Registers.
2021.11.17 21.3 Initial release.
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