F-Tile Dynamic Reconfiguration Design Example User Guide

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ID 710582
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Detailed Description for CPRI Multirate Design Example 3. Detailed Description for Ethernet Multirate Design Example 4. Detailed Description for Ethernet Multirate Design Example with Auto-Negotiation and Link Training Enabled 5. Detailed Description for PMA/FEC Direct PHY Multirate Design Example 6. Detailed Description for Ethernet to CPRI Design Example 7. F-Tile Dynamic Reconfiguration Design Example User Guide Archives 8. Document Revision History for the F-Tile Dynamic Reconfiguration Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Compiling the Compilation-Only Project 1.5. Simulating the Design Example Testbench 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Hardware Design Example
1.2. Generating the Design x
1.2.1. CPRI Multirate Design Example Parameters 1.2.2. Ethernet Multirate Design Example Parameters 1.2.3. PMA/FEC Direct PHY Multirate Design Example Parameters 1.2.4. Ethernet to CPRI Design Example Parameters
2. Detailed Description for CPRI Multirate Design Example x
2.1. CPRI Multirate Design Example: Functional Description 2.2. CPRI Multirate Design Example: Registers
2.1. CPRI Multirate Design Example: Functional Description x
2.1.1. CPRI Multirate Design Example: Simulation Testbench 2.1.2. CPRI Multirate Hardware Design Example 2.1.3. CPRI Multirate Design Example: Reset Scheme
3. Detailed Description for Ethernet Multirate Design Example x
3.1. Ethernet Multirate Design Example: Functional Description 3.2. Ethernet Multirate Design Example: Registers
3.1. Ethernet Multirate Design Example: Functional Description x
3.1.1. Ethernet Multirate Design Example: Simulation Testbench 3.1.2. Ethernet Multirate Hardware Design Example 3.1.3. Ethernet Multirate Design Example: Reset Scheme
4. Detailed Description for Ethernet Multirate Design Example with Auto-Negotiation and Link Training Enabled x
4.1. Ethernet Multirate Design Example with AN/LT Enabled: Functional Description
4.1. Ethernet Multirate Design Example with AN/LT Enabled: Functional Description x
4.1.1. AN/LT with Dynamic Reconfiguration Design Example Enhancement: User Logic 4.1.2. Ethernet Multirate Design Example with AN/LT Enabled: Simulation Testbench 4.1.3. Ethernet Multirate Hardware Design Example with AN/LT Enabled
4.1.1. AN/LT with Dynamic Reconfiguration Design Example Enhancement: User Logic x
4.1.1.1. Interfaces 4.1.1.2. Theory of Operation 4.1.1.3. Using Main.cpp file in User Logic 4.1.1.4. User Logic Modes 4.1.1.5. Hardware Testing in Suspend Mode 4.1.1.6. Simulation Testing in Suspend Mode
4.1.3. Ethernet Multirate Hardware Design Example with AN/LT Enabled x
4.1.3.1. Ethernet Multirate Design Example with AN/LT Enabled: Reset Scheme
5. Detailed Description for PMA/FEC Direct PHY Multirate Design Example x
5.1. PMA/FEC Direct PHY Multirate Design Example: Functional Description 5.2. PMA/FEC Direct PHY Multirate Design Example: Registers
5.1. PMA/FEC Direct PHY Multirate Design Example: Functional Description x
5.1.1. PMA/FEC Direct PHY Multirate Design Example: Simulation Testbench 5.1.2. PMA/FEC Direct PHY Multirate Hardware Design Example 5.1.3. PMA/FEC Direct Multirate Design Example: Reset Scheme
6. Detailed Description for Ethernet to CPRI Design Example x
6.1. Ethernet to CPRI Design Example: Functional Description 6.2. Ethernet to CPRI Design Example: Registers
6.1. Ethernet to CPRI Design Example: Functional Description x
6.1.1. Ethernet to CPRI Dynamic Reconfiguration Design Example: Simulation Testbench 6.1.2. Ethernet to CPRI Dynamic Reconfiguration Hardware Design Example 6.1.3. Ethernet to CPRI Dynamic Reconfiguration Design Example: Reset Scheme
1. Quick Start Guide
2. Detailed Description for CPRI Multirate Design Example
3. Detailed Description for Ethernet Multirate Design Example
4. Detailed Description for Ethernet Multirate Design Example with Auto-Negotiation and Link Training Enabled
5. Detailed Description for PMA/FEC Direct PHY Multirate Design Example
6. Detailed Description for Ethernet to CPRI Design Example
7. F-Tile Dynamic Reconfiguration Design Example User Guide Archives
8. Document Revision History for the F-Tile Dynamic Reconfiguration Design Example User Guide

6.2. Ethernet to CPRI Design Example: Registers

Table 22.  Address Map for Ethernet to CPRI Variant
Address Range Mapping
0x1000_0000 – 0x1000_FFFF P0 Ethernet Registers
0x1080_0000 – 0x108F_FFFF P0 Transceiver Registers
0x1010_0000 – 0x1010_FFFF 25G Packet Client
0x0000_0000 – 0x0000_03FF Dynamic Reconfiguration Controller
0x2000_0000 – 0x2000_003F CPRI Soft Registers
0x2010_0000 – 0x2010_FFFF CPRI PCS Registers
0x2020_0000 – 0x202F_FFFF CPRI Transceiver Registers
Table 23.  Address Map for Ethernet to CPRI Variant (with 1GE)
Address Range Mapping
0x1000_0000 – 0x1000_FFFF P0 Ethernet Registers
0x1080_0000 – 0x108F_FFFF P0 Transceiver Registers
0x1010_0000 – 0x1010_FFFF 25G Packet Client
0x0000_0000 – 0x0000_03FF Dynamic Reconfiguration Controller
0x2000_0000 – 0x2000_003F CPRI Soft Registers
0x2010_0000 – 0x2010_FFFF CPRI PCS Registers
0x2020_0000 – 0x202F_FFFF CPRI Transceiver Registers
0x3000_0000 - 0x3000_03FF 1G Ethernet (Triple-Speed Ethernet) Registers
0x3001_0000 - 0x3001_0FFF 1G Ethernet (Direct-PHY) soft CSR Registers. For more information, refer to F-Tile PMA/FEC Direct PHY Intel FPGA IP Core Soft CSR Registers.
0x3080_0000 - 0x308F_FFFF 1G Ethernet Transceiver Registers
0x3010_0000 - 0x3010_FFFF 1G Ethernet Traffic Controller
Table 24.  Address Map for Ethernet with PTP to CPRI Variant (with 1GE PTP)
Address Range Mapping
0x1000_0000 – 0x1000_FFFF P0 Ethernet Registers
0x1080_0000 – 0x108F_FFFF P0 Transceiver Registers
0x1010_0000 – 0x1010_FFFF 25G Packet Client
0x0000_0000 – 0x0000_03FF Dynamic Reconfiguration Controller
0x2000_0000 – 0x2000_003F CPRI Soft Registers
0x2010_0000 – 0x2010_FFFF CPRI PCS Registers
0x2020_0000 – 0x202F_FFFF CPRI Transceiver Registers
0x3000_0000 - 0x3000_03FF 1G Ethernet (Triple-Speed Ethernet) Registers
0x3001_0000 - 0x3001_0FFF 1G Ethernet (Direct-PHY) soft CSR Registers. For more information, refer to F-Tile PMA/FEC Direct PHY Intel FPGA IP Core Soft CSR Registers.
0x3080_0000 - 0x308F_FFFF 1G Ethernet Transceiver Registers
0x3010_0000 - 0x3010_FFFF 1G Ethernet Traffic Controller
0x3000_1000 - 0x3000_1FFF 1GE Ethernet TOD Master
0x3000_2000 - 0x3000_2FFF 1G Ethernet TX TOD
0x3000_3000 - 0x3000_3FFF 1G Ethernet RX TOD
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