AN 963: Intel® MAX® 10 Hitless Update Implementation Guidelines Using Internal JTAG Interface

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ID 710498
Date 4/21/2022
Public
Document Table of Contents
Document Table of Contents x
1. Intel® MAX® 10 DD Feature Option Devices Hitless Update Implementation Guidelines
1. Intel® MAX® 10 DD Feature Option Devices Hitless Update Implementation Guidelines x
1.1. Introduction 1.2. Hitless Update using Internal JTAG Interface 1.3. JTAG Instructions 1.4. Document Revision History for AN 963: Intel® MAX® 10 Hitless Update Implementation Guidelines Using Internal JTAG Interface
1.2. Hitless Update using Internal JTAG Interface x
1.2.1. Stages of Intel® MAX® 10 Hitless Update using Internal JTAG Interface 1.2.2. Internal JTAG Hitless Update Implementation Flow 1.2.3. Internal JTAG Hitless Update using Remote System Update Design Example
1. Intel® MAX® 10 DD Feature Option Devices Hitless Update Implementation Guidelines

1.2.2. Internal JTAG Hitless Update Implementation Flow

To implement the internal JTAG hitless update, perform the following steps on the user design:

  1. Execute SAMPLE/PRELOAD JTAG instruction using internal JTAG interface, shift in the desired I/O state or maintain the existing I/O state from the boundary scan.
  2. Execute CLAMP instruction using internal JTAG interface.
  3. Trigger reconfiguration using user logic with Dual Configuration Intel® FPGA IP.
  4. Wait for device initialization and internal configuration (refer to the Internal Configuration Time for Intel Devices (Uncompressed .rbf) and Internal Configuration Time for Intel Devices (Compressed .rbf) tables in the Intel FPGA Device Datasheet for internal configuration time).
  5. After entering user mode, you are recommended to perform JTAG TAP RESET to release the I/O clamp.
    Alternately, you may execute BYPASS instruction using internal JTAG interface to release the I/O clamp.
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