Intel® MAX® 10 devices offer the hitless update feature, which provides you the capability and flexibility to control the state of the I/O pins during the internal flash image update and reconfiguration of an Intel® MAX® 10 device. All of the I/O pins can remain stable without any disruption throughout the hitless update process. This feature also allows the Intel® MAX® 10 device to behave as a system controller when monitoring and controlling critical signals without interruption.

Intel® MAX® 10 devices with DD feature option offer an extension of hitless update with internal JTAG interface, in addition to using external JTAG pins. To support internal JTAG interface hitless update, the behavior of nSTATUS, nCONFIG, and CONF_DONE pins behavior are modified from controllable and observable to observable only.

These guidelines help you implement the hitless update using internal JTAG interface. This feature is only supported by Intel® MAX® 10 devices with DD feature option. For hitless update using external JTAG pins, refer to AN 904: Intel® MAX® 10 Hitless Update Implementation Guidelines.