AN 963: Intel® MAX® 10 Hitless Update Implementation Guidelines Using Internal JTAG Interface

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ID 710498
Date 4/21/2022
Public
Document Table of Contents
Document Table of Contents x
1. Intel® MAX® 10 DD Feature Option Devices Hitless Update Implementation Guidelines
1. Intel® MAX® 10 DD Feature Option Devices Hitless Update Implementation Guidelines x
1.1. Introduction 1.2. Hitless Update using Internal JTAG Interface 1.3. JTAG Instructions 1.4. Document Revision History for AN 963: Intel® MAX® 10 Hitless Update Implementation Guidelines Using Internal JTAG Interface
1.2. Hitless Update using Internal JTAG Interface x
1.2.1. Stages of Intel® MAX® 10 Hitless Update using Internal JTAG Interface 1.2.2. Internal JTAG Hitless Update Implementation Flow 1.2.3. Internal JTAG Hitless Update using Remote System Update Design Example
1. Intel® MAX® 10 DD Feature Option Devices Hitless Update Implementation Guidelines

1.3. JTAG Instructions

Table 1.  JTAG Instructions
Instruction Name Instruction Binary Description
SAMPLE/ PRELOAD 00 0000 0101
  • Permits an initial data pattern to be an output at the device pins.
  • Allows you to capture and examine a snapshot of signals at the device pins if the device is operating in normal mode.
EXTEST 00 0000 1111
  • Forces test pattern at the output pins and capture the test results at the input pins.
  • Allows you to test the external circuitry and board-level interconnects.
BYPASS 11 1111 1111
  • Places the 1-bit bypass register between the TDI and TDO pins.
  • Allows the BST data to pass synchronously through target devices to adjacent devices during normal device operation.
CLAMP 00 0000 1010
  • Places the 1-bit bypass register between the TDI and TDO pins. The 1-bit bypass register holds I/O pins to a state defined by the data in the boundary-scan register.
  • Allows the BST data to pass synchronously through target devices to adjacent devices if device is operating in normal mode.
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