At a high level, the implementation flow for Intel® MAX® 10 hitless update using internal JTAG interface may be categorized into five stages:

• Stage 1: Remote system update (RSU). Intel® MAX® 10 device is programmed with RSU image and enter user mode. Intel® MAX® 10 device internal flash (CFM and UFM) is then updated remotely with new application image while the design is still running.
• Stage 2: I/O clamp through boundary-scan. The I/O state is setup based on real-time I/O state sampling or by shifting in predefined boundary-scan data using internal JTAG interface to perform I/O clamp at the desired state. You may store critical design registers or finite state machine (FSM) values and the desired I/O state values into the UFM before performing Stage 2.
• Stage 3: Internal configuration. The I/Os remain in the desired state while the reconfiguration takes place from the internal flash into CRAM.
• Stage 4: Device initialization. After internal configuration is complete, the I/Os are released after entering user mode. You can unload the I/O state data, register, or FSM value that previously stored in the user flash memory, force the user design logic into a correct state to output the same desired I/O value as the clamping state, to ensure no disruption to the system.
• Stage 5: Normal user operation.