AN 963: Intel® MAX® 10 Hitless Update Implementation Guidelines Using Internal JTAG Interface

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ID 710498
Date 4/21/2022
Public
Document Table of Contents
Document Table of Contents x
1. Intel® MAX® 10 DD Feature Option Devices Hitless Update Implementation Guidelines
1. Intel® MAX® 10 DD Feature Option Devices Hitless Update Implementation Guidelines x
1.1. Introduction 1.2. Hitless Update using Internal JTAG Interface 1.3. JTAG Instructions 1.4. Document Revision History for AN 963: Intel® MAX® 10 Hitless Update Implementation Guidelines Using Internal JTAG Interface
1.2. Hitless Update using Internal JTAG Interface x
1.2.1. Stages of Intel® MAX® 10 Hitless Update using Internal JTAG Interface 1.2.2. Internal JTAG Hitless Update Implementation Flow 1.2.3. Internal JTAG Hitless Update using Remote System Update Design Example
1. Intel® MAX® 10 DD Feature Option Devices Hitless Update Implementation Guidelines

1.2. Hitless Update using Internal JTAG Interface

Create an Intel® Quartus® Prime user design that enables internal JTAG interface by including JTAG WYSIWYG atom. All four JTAG signals (TCK, TDI, TMS, and TDO) in the JTAG WYSIWYG atom need to be routed out to ensure the internal JTAG interfaces of Intel® MAX® 10 devices function correctly. Prior to hitless update, user design must first program the CFM with application image through FPGA core fabric and drive all I/Os to the desired state. Reconfiguration is triggered using user logic with Dual Configuration Intel® FPGA IP.

Section Content
Stages of Intel MAX 10 Hitless Update using Internal JTAG Interface
Internal JTAG Hitless Update Implementation Flow
Internal JTAG Hitless Update using Remote System Update Design Example

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