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1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel Agilex® 7 F-tile Devices
2. HDMI 2.1 Design Example (Support FRL = 1, Enable Active Video Protocol = None)
3. HDMI 2.1 Design Example with AXI4-stream Interface Enabled (Support FRL =1, Enable Active Video Protocol = AXIS-VVP Full)
4. Document Revision History for the F-Tile HDMI Intel® FPGA IP Design Example User Guide
2.1. Design Features
2.2. Hardware and Software Requirements
2.3. HDMI 2.1 RX-TX Retransmit Design Block Diagram
2.4. Design Parameters
2.5. Design Components
2.6. Design Software Flow
2.7. Clocking Scheme
2.8. Interface Signals
2.9. Hardware Setup
2.10. Simulation Testbench
2.11. Debugging Features
3.7.1. HDMI 2.1 RX-TX Retransmit Design without Video Frame Buffer (Enable Active Video Protocol = AXIS-VVP Full, Video In and Out Use the Same Clock = ON)
3.7.2. HDMI 2.1 RX-TX Retransmit Design with Video Frame Buffer (Enable Active Video Protocol = AXIS-VVP Full, Video In and Out Use the Same = OFF)
3.7.3. Clock Details
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Ixiasoft
3.9.1. Supporting Additional Video Resolutions
To support additional video resolutions, follow these steps:
- Modify the cvi_res_switch function in main.c software file to configure AXI2CV video mode bank to the desired resolution.
- For RX-TX restransmit design with video frame buffer:
- Modify the calc_frl_txclk function in the main software to add the correct TX video clock frequency configuration.
- Add the desired TV video clock frequency setting in set_txclk_freq function.
- Rebuild the software
- Open nios2 terminal.
- Change directory to /software/hdmi21_demo_app.
- Run <cmd>make</cmd>.