F-Tile HDMI Intel® FPGA IP Design Example User Guide

ID 709314
Date 8/15/2023

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Document Table of Contents

2. HDMI 2.1 Design Example (Support FRL = 1, Enable Active Video Protocol = None)

The HDMI 2.1 design example in FRL mode demonstrates one HDMI instance parallel loopback comprising four RX channels and four TX channels.
Table 7.   HDMI 2.1 Design Example for Intel Agilex® 7 F-tile Devices
Design Example Data Rate Channel Mode Loopback Type

Intel Agilex® 7 HDMI RX-TX Retransmit

  • 12 Gbps (FRL)
  • 10 Gbps (FRL)
  • 8 Gbps (FRL)
  • 6 Gbps (FRL)
  • 3 Gbps (FRL)
Simplex Parallel with FIFO buffer


This design offers the following features:
  • Instantiates FIFO buffers to perform a direct HDMI video stream passthrough between the HDMI 2.1 sink and source.
  • Comes with HDMI RX and TX instances.
  • Demonstrates the insertion and filtering of Dynamic Range and Mastering (HDR) InfoFrame in RX-TX link module.
  • Negotiates the FRL rate between the sink connected to TX and the source connected to RX. The design passes through the EDID from the external sink to the on-board RX in default configuration. The Nios® II processor negotiates the link base on the capability of the sink connected to TX. You can also toggle the user_dipsw on-board switch to manually control the TX and RX FRL capabilities.
  • Includes several debugging features.

This design variant currently only support FRL mode. Intel will enable support for TMDS mode in a future release.