F-Tile HDMI Intel® FPGA IP Design Example User Guide

ID 709314
Date 4/03/2023

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Document Table of Contents TX PHY Adapter

To support HDMI, TX PMA Direct PHY is configured to 64 bits parallel data width. Due to the HDMI TX inter-lane skew requirement for HDMI 1.4, HDMI 2.0 and HDMI 2.1, certain HDMI data rate needs to be oversampled to 24 Gbps to meet the inter-lane skew. Due to the maximum system clock frequency of 900 Mhz, the TX PHY needs to be configured to 64 bits (32 bits PMA width with byte serializer turned on) which result in the PMA clock of 750 Mhz.

In the TX PMA Direct PHY architecture with the system PLL, a DCFIFO is required to clock the TX parallel data from the link speed clock (data rate/effective transceiver width) to the system clock (sys_clk_div2) domain.

Figure 13. 80 bits to 128 bits Converter

An 80 bits to 128 bits converter is designed with four 80 bits register to store the TX parallel data from the TX core. The first 128 bits data is outputted after the 3rd clock cycle. After that, 128 bits data is outputted at the next five consecutive clock cycles. The process is repeated for every 8-clock cycle.