1.2. Generating the Design
Starting with the Nios® II Embedded Design Suite (EDS) in the Intel® Quartus® Prime Pro Edition software version 19.2 and Intel® Quartus® Prime Standard Edition software version 19.1, Intel has removed the Cygwin component in the Windows* version of Nios II EDS, replacing it with Windows Subsytem for Linux (WSL). If you are a Windows user, you need to install WSL prior to generating your design example.
- Create a project targeting the Intel Agilex® 7 device family with F-Tile, and select the desired device.
- In the IP Catalog, locate and double-click HDMI Intel FPGA IP. The New IP Variant or New IP Variation window appears.
- Specify a top-level name for your custom IP variation. The parameter editor saves the IP variation settings in a file named <your_ip>.ip .
- Click OK. The parameter editor appears.
- On the IP tab, configure the desired parameters for both TX or RX. Common parameters will be applied to both TX and RX.
- Support FRL is turned on by default to generate the HDMI 2.1 design example in FRL mode.
- On the Design Example tab, select Agilex 7 HDMI RX-TX Retransmit with clocked video interface.
- Select Simulation to generate the testbench, and select Synthesis to generate the hardware design example.
You must select at least one of these options to generate the design example files. If you select both, the generation time is longer.
Generation time for Synthesis will take about 30 minutes to allow ipgen.tcl process to qsys-generate a large number of PHY reconfig profiles and remove unused PHY sdc constraints, and speed up Fitter compilation time.
- For Generate File Format, select Verilog or VHDL.
- For Select Board, select the relevant development kit. You can change the target device using Change Target Device parameter if your board revision does not match the grade of the default targeted device. For the Intel Agilex® 7 FPGA I-Series Transceiver-SoC Development Kit, the default device is AGIB027R31B1E2VR0.
- Click Generate Example Design.
Table 4. Design Example Variant Generation Enable Active Video Protocol Video in and out use the same clock Design Example Variant None Not Applicable HDMI 2.1 RX-TX retransmit design on clocked video interface AXIS-VVP Full No HDMI 2.1 RX-TX retransmit design with video frame buffer on AXI4-stream interface AXIS-VVP Full Yes HDMI 2.1 RX-TX retransmit design without video frame buffer on AXI4-stream interface
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