F-Tile HDMI Intel® FPGA IP Design Example User Guide

ID 709314
Date 4/03/2023

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Document Table of Contents

2.1. Design Features

The design example supports the following features:
  • HDMI configuration of:
    • 8 pixel-in-parallel in video domain
    • 8 symbols per clock in FRL domain
  • FRL mode only
  • EDID passthrough mode only