F-Tile HDMI Intel® FPGA IP Design Example User Guide

ID 709314
Date 4/03/2023

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents RX PHY Adapter

HDMI RX core is configured to 40 bits in FRL mode while HDMI RX core is configured to 20 bits in TMDS model.

In FRL mode, HDMI RX core and RX PHY run at 40 bits width. In TMDS mode, HDMI RX core runs at 20 bits width. Since RX PHY is configured to 40bits, rdreq to DCFIFO is toggled every rx_clkout2 clock cycle to achieve half rate data.

Figure 16. Block Diagram for the FRL and TMDS Modes