F-Tile HDMI Intel® FPGA IP Design Example User Guide

ID 709314
Date 4/03/2023

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Document Table of Contents

3.8.1. Platform Design System

Signal Direction Width Description
cpu_clk_in_clk_clk Input 1 CPU clock. The frequency is 100 Mhz
cpu_rst_in_reset_reset Input 1 CPU reset
redriver_i2c_master_sda_in Input 1 I2C master interface to configure the external redriver setting
redriver_i2c_master_scl_in Input 1
redriver_i2c_master_sda_oe Output 1
redriver_i2c_master_scl_oe Output 1
txclk_i2c_master_sda_in Input 1 I2C master interface to configure the programmable oscillator to output TX video clock for RX-TX retransmit without video frame buffer design
txclk_i2c_master_scl_in Input 1
txclk_i2c_master_sda_oe Output 1
txclk_i2c_master_scl_oe Output 1
hdmi_rx_i2c_clk_clk Input 1 Clock input for DDC and SCDC interface. This clock is 100 Mhz
hdmi_rx_i2c_interface_scl Input 1 HDMI RX DDC and SCDC interface
hdmi_rx_i2c_interface_sda Input 1
hdmi_rx_hpd_interface_in_5v_power Input 1 HDMI RX 5V detect and hotplug detect. Refer to the Sink Interfaces section in HDMI Intel FPGA IP User Guide for more information
hdmi_rx_hpd_interface_hpd Output 1
hdmi_rx_av_mm_aux_out_aux_pkt_data Output 72

Auxiliary Memory Interface.

Refer to the Sink Interfaces section in HDMI Intel FPGA IP User Guide for more information

hdmi_rx_av_mm_aux_out_aux_pkt_addr Output 7
hdmi_rx_av_mm_aux_out_aux_pkt_wr Output 1
hdmi_tx_hpd_interface_hpd Input 1 HDMI TX Hot plug Detect interface
hdmi_tx_i2c_interface_scl Input 1 HDMI TX DDC and SCDC interface
hdmi_tx_i2c_interface_sda Input 1
hdmi_tx_audio_interface_audio_mute Input 1

HDMI TX Audio Mute control.

0 = Audio unmute

1 = Audio mute, audio data ignored

ddr4_emif_local_reset_req_local_reset_req Input 1

External Memory IP Interface (EMIF) for DDR4.

Refer to Section 4.1 of Intel Agilex® 7 EMIF IP Interface and Signal Descriptions of External Memory Interface Intel Agilex® 7 FPGA IP User Guide for more details.

Note: Only available when With Video Frame Buffer Design is selected.
ddr4_emif_local_reset_status_local_reset_done Output 1
ddr4_emif_pll_ref_clk_clk Input 1
ddr4_emif_oct_oct_rzqin Input 1
ddr4_emif_mem_mem_ck Output 1
ddr4_emif_mem_mem_ck_n Output 1
ddr4_emif_mem_mem_a Output 17
ddr4_emif_mem_mem_act_n Output 1
ddr4_emif_mem_mem_ba Output 2
ddr4_emif_mem_mem_bg Output 1
ddr4_emif_mem_mem_cke Output 1
ddr4_emif_mem_mem_cs_n Output 1
ddr4_emif_mem_mem_odt Output 1
ddr4_emif_mem_mem_reset_n Output 1
ddr4_emif_mem_mem_par Output 1
ddr4_emif_mem_mem_alert_n Input 1
ddr4_emif_mem_mem_dqs Input 9
ddr4_emif_mem_mem_dqs_n Input 9
ddr4_emif_mem_mem_dq Input 72
ddr4_emif_mem_mem_dbi_n Input 9
ddr4_emif_status_local_cal_success Output 1
ddr4_emif_status_local_cal_fail Output 1
dr_f_i_rst_n_reset_n Input 1 Dynamic Reconfig IP interface
dr_f_o_dr_curr_profile_id_o_dr_curr_profile_id Output 15
dr_f_o_dr_in_progress_o_dr_in_progress Output 1
dr_f_o_dr_error_status_o_dr_error_status Output 1
intel_hdmi_rx_phy_i2c_clk_clk Input 1 HDMI RX Transceiver Repackage Interface
intel_hdmi_rx_phy_rx_serial_data_wire1 Input 4
intel_hdmi_rx_phy_rx_serial_data_n_wire1 Input 4
intel_hdmi_rx_phy_phy_interface_hdmi_5v_detect_n Input 1
intel_hdmi_rx_phy_phy_interface_rx_5v_detect Output 1
intel_hdmi_rx_phy_phy_interface_device_ready Input 1
intel_hdmi_tx_phy_tx_serial_data_wire1 Output 4 HDMI TX Transceiver Repackage Interface
intel_hdmi_tx_phy_tx_serial_data_n_wire1 Output 4
intel_hdmi_tx_phy_tx_vid_clk_in_clk Input 1
intel_hdmi_tx_phy_phy_interface_device_ready Input 1
pll_vidclk_refclk_clk Input 1 IOPLL interface for video clock
systemclk_f_out_systempll_synthlock_0_out_systempll_synthlock Output 1 Transceiver SystemPLL clock interface
systemclk_f_refclk_fgt_in_refclk_fgt_0 Input 1
systemclk_f_refclk_fgt_in_refclk_fgt_1 Input 1
systemclk_f_refclk_fgt_in_refclk_fgt_2 Input 1

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