188.8.131.52.1. FRL and TMDS
In FRL and TMDS modes, HDMI TX core is running at 80 bits width. Since the TX PHY is configured to 64 bits width, you require an 80 bits to 128 bits converter and a mixed-width DCFIFO with 128 bits input and 64 bits output. In addition, in order to meet the inter-lane skew requirement, FRL data is oversampled twice. The TX PHY adapter comes with an oversample block to handle oversampling.
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