AN 940: Incremental Block-Based Compilation Tutorial: for Intel® Agilex™ F-Series FPGA Development Board

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ID 691276
Date 12/10/2021
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Document Table of Contents
Document Table of Contents x
1. AN 940: Incremental Block-Based Compilation Tutorial for Intel® Agilex™ F-Series FPGA Development Board
1. AN 940: Incremental Block-Based Compilation Tutorial for Intel® Agilex™ F-Series FPGA Development Board x
1.1. Tutorial Design Overview 1.2. Downloading Tutorial Design Files 1.3. Incremental Block-Based Compilation Tutorial 1.4. Document Revision History for AN 940: Incremental Block-Based Compilation Tutorial for Intel® Agilex™ FPGA Development Board
1.3. Incremental Block-Based Compilation Tutorial x
1.3.1. Step 1: Compile the Flat Design 1.3.2. Step 2: Identify Timing-Critical Design Blocks 1.3.3. Step 3: Create Design Partitions 1.3.4. Step 4: Analyze Timing of the Partitioned Design 1.3.5. Step 5: Preserve Timing-Closed Partitions 1.3.6. Step 6: Optimize Timing-Critical Design Blocks 1.3.7. Step 7: Verify Preservation and Optimized Results 1.3.8. (Optional) Step 8: Device Programming 1.3.9. (Optional) Step 9: Verify Results in Hardware
1. AN 940: Incremental Block-Based Compilation Tutorial for Intel® Agilex™ F-Series FPGA Development Board

1.1. Tutorial Design Overview

This tutorial includes a prepared design example to demonstrate use of incremental block-based compilation. You can download the design example to follow along with the tutorial steps in the Intel® Quartus® Prime Pro Edition software, as Downloading Tutorial Design Files describes.

The example top-level design instantiates a PLL that generates a 550 MHz fast clock (CLK1), and a 100 MHz slow clock (CLK2). The top-level design also instantiates 4 blinking LED modules that drive LED[3:0] every 2, 4, 8, and 16 seconds, respectively.

Figure 1. Incremental Block-Based Compilation Tutorial Design Example
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