AN 940: Incremental Block-Based Compilation Tutorial: for Intel® Agilex™ F-Series FPGA Development Board

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ID 691276
Date 12/10/2021
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Document Table of Contents
Document Table of Contents x
1. AN 940: Incremental Block-Based Compilation Tutorial for Intel® Agilex™ F-Series FPGA Development Board
1. AN 940: Incremental Block-Based Compilation Tutorial for Intel® Agilex™ F-Series FPGA Development Board x
1.1. Tutorial Design Overview 1.2. Downloading Tutorial Design Files 1.3. Incremental Block-Based Compilation Tutorial 1.4. Document Revision History for AN 940: Incremental Block-Based Compilation Tutorial for Intel® Agilex™ FPGA Development Board
1.3. Incremental Block-Based Compilation Tutorial x
1.3.1. Step 1: Compile the Flat Design 1.3.2. Step 2: Identify Timing-Critical Design Blocks 1.3.3. Step 3: Create Design Partitions 1.3.4. Step 4: Analyze Timing of the Partitioned Design 1.3.5. Step 5: Preserve Timing-Closed Partitions 1.3.6. Step 6: Optimize Timing-Critical Design Blocks 1.3.7. Step 7: Verify Preservation and Optimized Results 1.3.8. (Optional) Step 8: Device Programming 1.3.9. (Optional) Step 9: Verify Results in Hardware
1. AN 940: Incremental Block-Based Compilation Tutorial for Intel® Agilex™ F-Series FPGA Development Board

1.3.1. Step 1: Compile the Flat Design

Follow these steps to compile the flat (non-partitioned) design:
  1. In the Intel® Quartus® Prime Pro Edition software, click File > Open Project and open the /tutorial_flat/top.qpf project file.
  2. To compile the flat design, double-click Compile Design on the Compilation Dashboard. A check mark appears as each stage completes. The compilation may require 30 minutes or more, depending on your system.
    Figure 3. Compilation Dashboard

By default, the Timing Analyzer opens automatically and loads the Final timing netlist.

Figure 4.  Intel® Quartus® Prime Timing Analyzer
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