AN 940: Incremental Block-Based Compilation Tutorial: for Intel® Agilex™ F-Series FPGA Development Board

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ID 691276
Date 12/10/2021
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Document Table of Contents x
1. AN 940: Incremental Block-Based Compilation Tutorial for Intel® Agilex™ F-Series FPGA Development Board
1. AN 940: Incremental Block-Based Compilation Tutorial for Intel® Agilex™ F-Series FPGA Development Board x
1.1. Tutorial Design Overview 1.2. Downloading Tutorial Design Files 1.3. Incremental Block-Based Compilation Tutorial 1.4. Document Revision History for AN 940: Incremental Block-Based Compilation Tutorial for Intel® Agilex™ FPGA Development Board
1.3. Incremental Block-Based Compilation Tutorial x
1.3.1. Step 1: Compile the Flat Design 1.3.2. Step 2: Identify Timing-Critical Design Blocks 1.3.3. Step 3: Create Design Partitions 1.3.4. Step 4: Analyze Timing of the Partitioned Design 1.3.5. Step 5: Preserve Timing-Closed Partitions 1.3.6. Step 6: Optimize Timing-Critical Design Blocks 1.3.7. Step 7: Verify Preservation and Optimized Results 1.3.8. (Optional) Step 8: Device Programming 1.3.9. (Optional) Step 9: Verify Results in Hardware
1. AN 940: Incremental Block-Based Compilation Tutorial for Intel® Agilex™ F-Series FPGA Development Board

1.3.8. (Optional) Step 8: Device Programming

You can optionally configure the FPGA on the Intel® Agilex™ Development Kit to verify the results in hardware. You can adapt the following steps if you are using a different device or development kit.
Configuring the FPGA involves opening the Intel® Quartus® Prime Pro Edition Programmer, connecting to the Development Kit board, and loading the configuration SRAM Object File (.sof) into the SRAM of the FPGA.
Note: A .sof file configures the SRAM of an Intel® FPGA. A Programmer Object File (.pof) programs a flash memory device with an FPGA configuration image for subsequent loading to an FPGA.

Follow these steps to configure the FPGA on the Intel® Agilex™ Development Kit:

  1. To open the Intel® Quartus® Prime Programmer, click Tools > Programmer.
  2. Connect the board cables:
    • JTAG USB cable to board
    • Power cable attached to board and power source
  3. Turn on power to the board.
  4. In the Intel® Quartus® Prime Programmer, click Hardware Setup.
    Figure 13. Hardware Setup
  5. In the Hardware list, select USB-BlasterII, and then click Close. The device chain appears.
    Note: If the device chain does not appear, verify the board connections.
  6. Click Auto-Detect. The device chain populates.
  7. In the Found Devices list, select the device that matches your design and click OK. For this tutorial, select the AGFB014R24AR0 device that matches the <FPGA ID to be updated> FPGA on the Intel® Agilex™ Development Kit.
    Figure 14. Select Device
  8. Right-click the AGFB014R24AR0 row in the file list, and then click Change File.
  9. Browse to select the top.sof file from the appropriate tutorial/output_files/ directory.
  10. Enable the Program/Configure option for the AGFB014R24AR0 row.
    Figure 15. Program/Configure Option
  11. Click Start. The progress bar reaches 100% when device configuration is complete. The device is now fully configured and in operation.
    Figure 16. Programming Successful
    Note: If device configuration fails, make sure the device you select for configuration matches the device you specify during .sof file generation.
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