AN 940: Incremental Block-Based Compilation Tutorial: for Intel® Agilex™ F-Series FPGA Development Board
ID
691276
Date
12/10/2021
Public
1.3.1. Step 1: Compile the Flat Design
1.3.2. Step 2: Identify Timing-Critical Design Blocks
1.3.3. Step 3: Create Design Partitions
1.3.4. Step 4: Analyze Timing of the Partitioned Design
1.3.5. Step 5: Preserve Timing-Closed Partitions
1.3.6. Step 6: Optimize Timing-Critical Design Blocks
1.3.7. Step 7: Verify Preservation and Optimized Results
1.3.8. (Optional) Step 8: Device Programming
1.3.9. (Optional) Step 9: Verify Results in Hardware
1.3.3. Step 3: Create Design Partitions
After identifying the timing-critical design blocks, you partition and recompile the design to preserve the results for partitions that meet timing.
Create Design Partitions
- In the Project Navigator, right-click u_blinking_led_i1 in the Hierarchy tab, point to Design Partition, and select the Default partition Type. A design partition icon appears next to each instance you assign.
- Repeat step 1 to create partitions for the u_big_partition1_top, u_blinking_led_i2, u_blinking_led_i3, and u_blinking_led_i4 instances.
- Click Assignments > Design Partitions Window to open. The Design Partitions Window lists the partitions you define, along with the root partition (|) the Compiler automatically creates for each project.
Figure 7. Design Partitions Window
- To compile the partitioned design, double-click Compile Design on the Compilation Dashboard.
The Timing Analyzer opens automatically following compilation.