AN 940: Incremental Block-Based Compilation Tutorial: for Intel® Agilex™ F-Series FPGA Development Board
ID
691276
Date
12/10/2021
Public
1.3.1. Step 1: Compile the Flat Design
1.3.2. Step 2: Identify Timing-Critical Design Blocks
1.3.3. Step 3: Create Design Partitions
1.3.4. Step 4: Analyze Timing of the Partitioned Design
1.3.5. Step 5: Preserve Timing-Closed Partitions
1.3.6. Step 6: Optimize Timing-Critical Design Blocks
1.3.7. Step 7: Verify Preservation and Optimized Results
1.3.8. (Optional) Step 8: Device Programming
1.3.9. (Optional) Step 9: Verify Results in Hardware
1.3.7. Step 7: Verify Preservation and Optimized Results
After compilation is complete, follow these steps to verify that the Compiler uses the preserved partitions, and that the optimized design block now meets timing requirements:
- In the Compilation Report (Processing > Compilation Report), under the Fitter folder, expand the Preserved Assignments folder. The reports indicate use of the preserved partitions.
Figure 11. Preserved Partitions Report
- Click Tools > Timing Analyzer , and then double-click Update Timing Netlist.
- Run the report_timing.tcl script to regenerate the timing analysis reports:
Timing analysis data in the inst_i4 report folder now indicates that the blinking_led_i4 partition meets timing requirements.source report_timing.tcl
Figure 12. Optimized u_blinking_led_i4 Meets Timing - Click the inst_i4 report in the Report pane. Also check the slack and placement results for the big_partition1_top, blinking_led_i1, blinking_led_i2, and blinking_led_i3 partitions. The slack value is similar to performance at the time of preservation. The placement results are the same as at the time of preservation.