AN 940: Incremental Block-Based Compilation Tutorial: for Intel® Agilex™ F-Series FPGA Development Board

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ID 691276
Date 12/10/2021
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Document Table of Contents x
1. AN 940: Incremental Block-Based Compilation Tutorial for Intel® Agilex™ F-Series FPGA Development Board
1. AN 940: Incremental Block-Based Compilation Tutorial for Intel® Agilex™ F-Series FPGA Development Board x
1.1. Tutorial Design Overview 1.2. Downloading Tutorial Design Files 1.3. Incremental Block-Based Compilation Tutorial 1.4. Document Revision History for AN 940: Incremental Block-Based Compilation Tutorial for Intel® Agilex™ FPGA Development Board
1.3. Incremental Block-Based Compilation Tutorial x
1.3.1. Step 1: Compile the Flat Design 1.3.2. Step 2: Identify Timing-Critical Design Blocks 1.3.3. Step 3: Create Design Partitions 1.3.4. Step 4: Analyze Timing of the Partitioned Design 1.3.5. Step 5: Preserve Timing-Closed Partitions 1.3.6. Step 6: Optimize Timing-Critical Design Blocks 1.3.7. Step 7: Verify Preservation and Optimized Results 1.3.8. (Optional) Step 8: Device Programming 1.3.9. (Optional) Step 9: Verify Results in Hardware
1. AN 940: Incremental Block-Based Compilation Tutorial for Intel® Agilex™ F-Series FPGA Development Board

1.3.4. Step 4: Analyze Timing of the Partitioned Design

Follow these steps to analyze the timing of the partitioned design:
  1. Run the report_timing.tcl script from the console to regenerate the timing analysis reports for failing paths: 
    source report_timing.tcl
    Figure 8. u_blinking_led_i4 Violates Timing Requirements
    The timing analysis reports in the inst_i4 folder remain red, indicating that u_blinking_led_i4 still does not meet timing requirements in the partitioned design. Later in this tutorial you optimize these design blocks to ensure that they meet timing requirements in the flat design.
  2. Right-click the inst_big report, and then click Regenerate.
    Figure 9.  u_big_partition1_top Report
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