AN 940: Incremental Block-Based Compilation Tutorial: for Intel® Agilex™ F-Series FPGA Development Board
ID
691276
Date
12/10/2021
Public
1.3.1. Step 1: Compile the Flat Design
1.3.2. Step 2: Identify Timing-Critical Design Blocks
1.3.3. Step 3: Create Design Partitions
1.3.4. Step 4: Analyze Timing of the Partitioned Design
1.3.5. Step 5: Preserve Timing-Closed Partitions
1.3.6. Step 6: Optimize Timing-Critical Design Blocks
1.3.7. Step 7: Verify Preservation and Optimized Results
1.3.8. (Optional) Step 8: Device Programming
1.3.9. (Optional) Step 9: Verify Results in Hardware
1.3.5. Step 5: Preserve Timing-Closed Partitions
You can preserve the final snapshot of the partitions that meet timing requirements, to retain the same implementation in subsequent compilations.
You do not preserve the final snapshot for blinking_led_8s and blinking_led_16s because these are failing timing.
The Compiler preserves the final device utilization, placement, routing, and hold time fix-up for the partitions that you preserve. The preserved partition becomes the source for each subsequent compilation.
Follow these steps to preserve the timing-closed partitions:
- Click Assignments > Design Partitions Window.
- Select final as the Preservation Level for the blinking_led_2s, big_partition1_top, blinking_led_4s, and blinking_led_8s partitions.
Figure 10. Setting Partition Preservation Levels