F-Tile JESD204C Intel® FPGA IP User Guide

ID 691272
Date 4/11/2023

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5.1. Reset Initialization

The F-Tile JESD204C base core and transport layer require various resets for the IP and transceiver. All the resets in the core assert asynchronously and deassert synchronously.
Table 14.   F-Tile JESD204C IP Resets
Reset Signal Clock Domain Description



Asynchronous Assertion of these signals resets all logic in the IP (MAC, TL, FIFOs).



TX/RX Avalon® memory-mapped reset for CSR


  • This reset is for the Avalon® memory-mapped slave interface, which consists of the Configuration and Status Register (CSR) blocks.
  • After this reset deasserts, configuration phase starts. You can program the CSR register values if a non-default value is required.



Asynchronous These signals acknowledge the state of j204c_tx_rst_n and j204c_rx_rst_n. The reset sequence completion is indicated by the assertion of these signals.
reconfig_xcvr_reset Asynchronous

Transceiver reconfiguration clock.

Active high signal. During duplex mode, both TX and RX share the same reconfiguration pins.

Intel recommends that you tie this signal to tx_avs_rst_n.