The F-Tile JESD204C TX and RX IP core support scrambling by implementing a 64-bit parallel scrambler in each lane. The scrambler and descrambler are located in the F-Tile JESD204C IP MAC interfacing to the Avalon® streaming interface. You can enable or disable scrambling through CSR configuration for all lanes. Mixed mode operation, where scrambling is enabled for some lanes, is not permitted.
The scrambling polynomial is:
x58 + x39 + 1