F-Tile JESD204C Intel® FPGA IP User Guide

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ID 691272
Date 4/11/2023
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Document Table of Contents
Document Table of Contents x
1. About the F-Tile JESD204C Intel® FPGA IP User Guide 2. Overview of the F-Tile JESD204C Intel® FPGA IP 3. Functional Description 4. Getting Started 5. Designing with the F-Tile JESD204C Intel® FPGA IP 6. F-Tile JESD204C Intel® FPGA IP Parameters 7. Interface Signals 8. Control and Status Registers 9. F-Tile JESD204C Intel® FPGA IP User Guide Archives 10. Document Revision History for the F-Tile JESD204C Intel® FPGA IP User Guide
2. Overview of the F-Tile JESD204C Intel® FPGA IP x
2.1. Release Information 2.2. Device Family Support 2.3. F-Tile JESD204C Intel® FPGA IP Features 2.4. Performance and Resource Utilization
3. Functional Description x
3.1. Clocks 3.2. Local Extended Multiblock Clock 3.3. CRC Encoding/Decoding 3.4. Scrambler/Descrambler
3.1. Clocks x
3.1.1. Device Clock 3.1.2. Frame Clock and Link Clock 3.1.3. System PLL
3.2. Local Extended Multiblock Clock x
3.2.1. LEMC Counter
4. Getting Started x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Intel® FPGA IP Evaluation Mode 4.3. IP Catalog and Parameter Editor 4.4. F-Tile JESD204C IP Component Files 4.5. Creating a New Intel® Quartus® Prime Project 4.6. Parameterizing and Generating the IP 4.7. Compiling the F-Tile JESD204C IP Design 4.8. Programming an FPGA Device
5. Designing with the F-Tile JESD204C Intel® FPGA IP x
5.1. Reset Initialization 5.2. Configuration Phase 5.3. Link Reinitialization 5.4. SYSREF Sampling 5.5. Interrupt and Error Handling 5.6. Multi-Device Synchronization 5.7. Deterministic Latency 5.8. Transceiver Toolkit
5.1. Reset Initialization x
5.1.1. F-Tile JESD204C TX Reset Sequence 5.1.2. F-Tile JESD204C RX Reset Sequence
5.5. Interrupt and Error Handling x
5.5.1. Interrupt Configuration for TX and RX 5.5.2. Interrupt Top Half ISR Handler 5.5.3. Interrupt Bottom Half ISR Handler
5.6. Multi-Device Synchronization x
5.6.1. Multi-Device DAC Application for Subclass 1 5.6.2. Multi-Device ADC Application for Subclass 1
5.7. Deterministic Latency x
5.7.1. RBD Tuning Mechanism
7. Interface Signals x
7.1. Transmitter Signals 7.2. Receiver Signals
8. Control and Status Registers x
8.1. Transmitter and Receiver Registers
1. About the F-Tile JESD204C Intel® FPGA IP User Guide
2. Overview of the F-Tile JESD204C Intel® FPGA IP
3. Functional Description
4. Getting Started
5. Designing with the F-Tile JESD204C Intel® FPGA IP
6. F-Tile JESD204C Intel® FPGA IP Parameters
7. Interface Signals
8. Control and Status Registers
9. F-Tile JESD204C Intel® FPGA IP User Guide Archives
10. Document Revision History for the F-Tile JESD204C Intel® FPGA IP User Guide

5.5.3. Interrupt Bottom Half ISR Handler

The bottom half ISR handler mainly controls a chain of events to the SPI controller device or clock chips, and the F-Tile JESD204C IP.

The following tables describe the ISR handler recommendations for different TX and RX error types.

Table 15.  TX Interrupt Handler Recommendations
Error Type ISR Handler Operation
tx_sysref_lemc_err
  • This error occurs when the SYSREF signal continuously resets the LEMC counter at an unexpected time, which violates the LEMC period.
  • The processor needs to check the setting for all LEMC counters configured on the F-Tile JESD204C IP converter device and clock chip.
tx_dll_data_invalid_err
  • This error occurs when data bubble appears on the Avalon® streaming interface in the F-Tile JESD204C TX base core.
  • The processor needs to probe the upstream device the find out why it has stalled and take further action.
Note: By design, you should calculate the data throughput to ensure that there are no data bubbles in the design. This additional protection is to minimize errors in the system.
tx_frame_data_invalid_err
  • This error occurs when data bubble appears on the Avalon® streaming interface in the F-Tile JESD204C TX transport layer.
  • The processor needs to probe the upstream device the find out why it has stalled and take further action.
Note: By design, you should calculate the data throughput to ensure that there are no data bubbles in the design. This additional protection is to minimize errors in the system.
cmd_invalid_err
  • This error occurs when data bubble appears on the Avalon® streaming command interface in the F-Tile JESD204C TX link layer.
  • The processor needs to probe the upstream device the find out why it has stalled and take further action.
Note: By design, you should calculate the data throughput to ensure that there are no data bubbles in the design. This additional protection is to minimize errors in the system.
tx_gb_underflow_err
  • This error is flagged when at least 1 instance of the TX gearbox FIFO is having underflow.
  • The processor ensures that the system design provides the correct j204c_txlink_clk frequency of (data rate)/66 to the IP.
tx_gb_overflow_err
  • This error is flagged when at least 1 instance of the TX gearbox FIFO is having overflow.
  • The processor ensures that the system design provides the correct j204c_txlink_clk frequency of (data rate)/66 to the IP.
efifo_overflow_err
  • This error is flagged when an overflow happens in any of the lane's TX eFIFOs.
  • The processor ensures that the system design provides system PLL clock sysclk is equal or higher than native clock frequency.
src_tx_alarm
  • This error is flagged when the F-tile's soft reset controller generates a TX alarm.
  • The processor ensures the refclk supply to transceiver is accurate.
syspll_lock_err
  • This error is flagged when the system PLL loses lock while the F-Tile JESD204C link is up and running.
  • The processor ensures that the refclk to external system PLL is accurate.
tx_pll_lock_err
  • This error is flagged when one or more lanes of the transceiver TX PLL looses lock while the F-Tile JESD204C link is up and running.
  • The processor ensures that refclk supply to transceiver is accurate.
Table 16.  RX Interrupt Handler Recommendations
Error Type ISR Handler Operation
rx_sysref_lemc_err
  • This error occurs when the SYSREF signal continuously resets the LEMC counter at an unexpected time, which violates the LEMC period.
  • The processor needs to check the setting for all LEMC counters configured on the F-Tile JESD204C IP converter device and clock chip.
  • By default, the link automatically reinitializes when this signal is asserted.
rx_dll_data_ready_err
  • This error occurs when the Avalon® streaming interface in the F-Tile JESD204C RX base core does not have backpressure and yet, the upstream device indicates that it is unable to take in data.
  • The processor needs to probe the upstream device to find out why it has stalled and take further action.
Note: By design, you should calculate the data throughput to ensure that there are no data bubbles in the design. This additional protection is to minimize errors in the system.
rx_frame_data_ready_err
  • This error occurs when the Avalon® streaming interface in the RX transport layer does not have backpressure and yet, the upstream device indicates that it is unable to take in data.
  • The processor needs to probe the upstream device to find out why it has stalled and take further action.
Note: By design, you should calculate the data throughput to ensure that there are no data bubbles in the design. This additional protection is to minimize errors in the system.
rx_cmd_ready_err
  • This error occurs when the Avalon® streaming command interface in the RX link layer does not have backpressure and yet, the upstream device indicates that it is unable to take in data.
  • The processor needs to probe the upstream device to find out why it has stalled and take further action.
Note: By design, you should calculate the data throughput to ensure that there are no data bubbles in the design. This additional protection is to minimize errors in the system.
rx_cdr_locked_err
  • This error occurs because of incoming data stream that causes RX PMA to unlock its CDR.
  • The processor may not be able to recover from such error. PMA debug is required.
rx_lane_deskew_err
  • This is a system error.
  • You need to investigate total skew and the E parameter settings.
rx_invalid_sync_header
  • This error occurs when the IP receives “00” or “11” in the expected SH location.
  • Refer to the JESD204C Specifications for action required for hardware.
rx_invalid_eomb
  • This errors occurs when “00001” sequence in the pilot signal is not received at an expected location in the sync word.
  • Refer to the JESD204C Specifications for action required for hardware.
rx_invalid_eoemb
  • This error occurs when the EoEMB identifier in the pilot signal has an unexpected value.
  • Refer to the JESD204C Specifications for action required for hardware.
rx_cmd_par_err
  • The error is flagged when the final parity bit in the command channel data for a given Sync Word does not match the calculated parity for the received command channel bits.
  • Refer to the JESD204C Specifications for action required for hardware.
rx_crc_err
  • This error occurs when the receive CRC generator has calculated a parity which does not match the parity received in the Sync Word.
  • The hardware tries to reinitialize but if the error persists, the processor is required to find out the cause of CRC error.
rx_gb_underflow_err
  • This error is flagged when at least 1 instance of the RX gearbox FIFO is having underflow.
  • This underflow error occurs when the frequency ratio between j204c_rxlink_clk and j204_rxphy_clk is larger than 16:33. In this scenario, the j204c_rxlink_clk clock is unexpectedly faster than the j204c_rxphy_clk clock.
  • When this error occurs, the system needs to reset.
  • To prevent this error from occurring, the frequency ratio of j204c_rxlink_clk and j204_rxphy_clk must be 16:33.
rx_gb_overflow_err
  • This error is flagged when at least 1 instance of the RX gearbox is having overflow.
  • This overflow error occurs when the frequency ratio between j204c_rxlink_clk and j204_rxphy_clk is smaller than 16:33. In this scenario, the j204c_rxlink_clk clock is unexpectedly slower than the j204c_rxphy_clk clock.
  • When this error occurs, the system needs to reset.
  • To prevent this error from occurring, the frequency ratio of j204c_rxlink_clk and j204_rxphy_clk must be 16:33.
rx_sh_unlock_err
  • This error indicates that SH alignment is lost.
  • The hardware always tries to reinitialize for this error.
rx_emb_unlock_err
  • This error indicates that EMB alignment is lost.
  • The hardware always tries to reinitialize for this error.
rx_eb_full_err
  • This error could be caused by the same reason that causes deskew error.
  • You need to investigate total skew and the E parameter settings.
rx_ecc_corrected_err
  • This error keeps track of the EC detected. Intel recommends you to enable this error so that the processor can keep track of the EC detected.
  • The processor can enter error detection and correction routine.
rx_ecc_fatal_err
  • ECC fatal error that indicates bad data has been sent to the upstream device. The severity of this error depends on the system.
  • For example, ultrasound applications may still cope with uncorrectable ECC errors. However, systems where data packets should never be lost, the system may reset the core.
src_rx_alarm
  • This error is flagged when the F-tile's soft reset controller generates a RX alarm.
  • The processor ensures the refclk supply to transceiver is accurate.
syspll_lock_err
  • This error is flagged when the system PLL loses lock while the F-Tile JESD204C link is up and running.
  • The processor ensures that the refclk to external system PLL is accurate.
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