4.7. Compiling the F-Tile JESD204C IP Design
Refer to the Designing with the F-Tile JESD204C Intel FPGA IP before compiling the F-Tile JESD204C IP core design.
To compile your design, click Start Compilation on the Processing menu in the Intel® Quartus® Prime software. You can use the generated .ip or .qip file to include relevant files into your project.
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