F-Tile JESD204C Intel® FPGA IP User Guide

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ID 691272
Date 4/11/2023
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Document Table of Contents
Document Table of Contents x
1. About the F-Tile JESD204C Intel® FPGA IP User Guide 2. Overview of the F-Tile JESD204C Intel® FPGA IP 3. Functional Description 4. Getting Started 5. Designing with the F-Tile JESD204C Intel® FPGA IP 6. F-Tile JESD204C Intel® FPGA IP Parameters 7. Interface Signals 8. Control and Status Registers 9. F-Tile JESD204C Intel® FPGA IP User Guide Archives 10. Document Revision History for the F-Tile JESD204C Intel® FPGA IP User Guide
2. Overview of the F-Tile JESD204C Intel® FPGA IP x
2.1. Release Information 2.2. Device Family Support 2.3. F-Tile JESD204C Intel® FPGA IP Features 2.4. Performance and Resource Utilization
3. Functional Description x
3.1. Clocks 3.2. Local Extended Multiblock Clock 3.3. CRC Encoding/Decoding 3.4. Scrambler/Descrambler
3.1. Clocks x
3.1.1. Device Clock 3.1.2. Frame Clock and Link Clock 3.1.3. System PLL
3.2. Local Extended Multiblock Clock x
3.2.1. LEMC Counter
4. Getting Started x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Intel® FPGA IP Evaluation Mode 4.3. IP Catalog and Parameter Editor 4.4. F-Tile JESD204C IP Component Files 4.5. Creating a New Intel® Quartus® Prime Project 4.6. Parameterizing and Generating the IP 4.7. Compiling the F-Tile JESD204C IP Design 4.8. Programming an FPGA Device
5. Designing with the F-Tile JESD204C Intel® FPGA IP x
5.1. Reset Initialization 5.2. Configuration Phase 5.3. Link Reinitialization 5.4. SYSREF Sampling 5.5. Interrupt and Error Handling 5.6. Multi-Device Synchronization 5.7. Deterministic Latency 5.8. Transceiver Toolkit
5.1. Reset Initialization x
5.1.1. F-Tile JESD204C TX Reset Sequence 5.1.2. F-Tile JESD204C RX Reset Sequence
5.5. Interrupt and Error Handling x
5.5.1. Interrupt Configuration for TX and RX 5.5.2. Interrupt Top Half ISR Handler 5.5.3. Interrupt Bottom Half ISR Handler
5.6. Multi-Device Synchronization x
5.6.1. Multi-Device DAC Application for Subclass 1 5.6.2. Multi-Device ADC Application for Subclass 1
5.7. Deterministic Latency x
5.7.1. RBD Tuning Mechanism
7. Interface Signals x
7.1. Transmitter Signals 7.2. Receiver Signals
8. Control and Status Registers x
8.1. Transmitter and Receiver Registers
1. About the F-Tile JESD204C Intel® FPGA IP User Guide
2. Overview of the F-Tile JESD204C Intel® FPGA IP
3. Functional Description
4. Getting Started
5. Designing with the F-Tile JESD204C Intel® FPGA IP
6. F-Tile JESD204C Intel® FPGA IP Parameters
7. Interface Signals
8. Control and Status Registers
9. F-Tile JESD204C Intel® FPGA IP User Guide Archives
10. Document Revision History for the F-Tile JESD204C Intel® FPGA IP User Guide

2.3. F-Tile JESD204C Intel® FPGA IP Features

The F-Tile JESD204C Intel® FPGA IP is a high-speed point-to-point serial interface intellectual property (IP). The F-Tile JESD204C Intel® FPGA IP is the latest IP from Intel that supports the F-Tile JESD204C protocol. This IP is not backwards compatible and does not support JESD204B protocol. You can use the existing the JESD204B Intel® FPGA IP to support JESD204B protocol.

Table 6.  Brief Information about the F-Tile JESD204C Intel® FPGA IP

Features

Description

Protocol Features

  • Joint Electron Device Engineering Council (JEDEC) F-Tile JESD204C standard 2017
  • Device subclass:
    • Subclass 0—No deterministic latency
    • Subclass 1—Uses SYSREF signal to support deterministic latency

Core Features

  • Data rate of up to 32.44032 Gbps for Intel® Agilex™ 7 (F-tile) devices
  • Single or multiple lanes (up to 16 lanes per link)
  • Local extended multiblock clock (LEMC) counter based on E = 1 to 32
  • Supports F = 1 to 256 octets per frame
  • Serial lane alignment and monitoring
  • Lane synchronization
  • Modular design that supports multidevice synchronization
  • MAC and PHY partitioning
  • Deterministic latency support
  • Interrupts and error handling support
  • System PLL clocking
  • 64/66 encoding
  • Scrambling/descrambling
  • Avalon® streaming interface for transmit and receive datapaths
  • Avalon® memory-mapped interface for control and status registers (CSR)
  • Dynamic generation of simulation testbench
  • Bonded and non-bonded TX PMA mode
  • Optional support for ECC M20K DCFIFO
  • Support for Transceiver Toolkit for PMA using embedded Native PHY Debug Master Endpoint (NPDME)
  • Options for sync header configurations
    • CRC-12
    • Standalone command channels
Limitations No FEC support

Typical Application

  • Wireless communication equipment
  • Broadcast equipment
  • Military equipment
  • Medical equipment
  • Test and measurement equipment

Device Family Support

  • Intel® Agilex™ 7 (F-tile) FPGA devices

Design Tools

  • Platform Designer parameter editor in the Intel® Quartus® Prime Pro Edition software for design creation and compilation

  • Timing Analyzer in the Intel® Quartus® Prime software for timing analysis

  • QuestaSim* , ModelSim* - Intel® FPGA Starter Edition, and VCS* / VCS* MX simulator software for design simulation or synthesis
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