AN 696: Using the JESD204B MegaCore Function in Arria V Devices

ID 683843
Date 5/11/2015
Public

1.4. Using the Reference Design

This section describes a high-level flow of how to use the reference design files in the Quartus II software.
  1. Extract the reference design's archive file from avgt_jesd204b_ad9250_ed.zip.
  2. Launch the Quartus II software.
  3. On the File menu, click Open.
  4. Navigate to your project directory and select the avgt_jesd204b_ad9250_ed_<Quartus II version>.qar file. Click Open.
  5. In the Restore Archived Project window, set the archive file name and destination folder. Click OK.
  6. To download the .sof file and program the FPGA device on the development board, perform the following steps:
    1. On the Tools menu, click Programmer.
    2. Click Add File.
    3. Navigate to <project directory> \<output_files>\jesd204b_ed_golden.sof and click Open.
    4. Click Start to download the file into the FPGA device on the development board.
  7. Use the System Console tool to reset the system and trigger an initialization for the JESD204B MegaCore function link.

Optionally, if you want to edit the JESD204B MegaCore function parameters and recompile the reference design, refer to the section on section.

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