AN 696: Using the JESD204B MegaCore Function in Arria V Devices

ID 683843
Date 5/11/2015
Public

1.3.2. Status LED

The table below lists the status LEDs on the Arria V GT FPGA Development Kit and its function.
Note: If you utilize the Signal Tap II Logic Analyzer tool to pole the status of these signals, use the rxframe_clk signal as the sampling clock.
Table 7.  Status LEDs
LED Board Reference Signal Name Description
D26 data_error [1:0] Single AND-ed error status signal for the PRBS checkers from both lane 0 & lane 1. The LED illuminates to indicate a data error.
D27 jesd204_tx_int Link layer TX interrupt signal. Applicable only when internal serial loopback is enabled. The LED illuminates to indicate a TX interrupt.
D28 jesd204_rx_int Link layer RX interrupt signal. The LED illuminates to indicate a RX interrupt.
D29 rx_dev_sync_n SYNC~ signal to the transmitter. The LED illuminates to indicate that the transmitter has received K28.5 characters.
D30 dev_lane_aligned RX path lane alignment status signal for the device. The LED illuminates to indicate that lane alignment is achieved.
D31 avs_rst_n Link layer CSR Avalon-MM reset signal. The LED illuminates to indicate that the Avalon-MM interface is out of reset.
D32 link_rst_n Link layer reset signal. The LED illuminates to indicate that the link layer is out of reset.
D33 frame_rst_n Transport layer reset signal. The LED illuminates to indicate that the transport layer is out of reset.

Did you find the information on this page useful?

Characters remaining:

Feedback Message