AN 696: Using the JESD204B MegaCore Function in Arria V Devices

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ID 683843
Date 5/11/2015
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Document Table of Contents
Document Table of Contents x
1. AN 696: Using the JESD204B MegaCore Function in Arria V Devices
1. AN 696: Using the JESD204B MegaCore Function in Arria V Devices x
1.1. JESD204B MegaCore Function Reference Design 1.2. Hardware and Software Requirements 1.3. Hardware Setup 1.4. Using the Reference Design 1.5. Using the System Console Tool to Execute Commands 1.6. JESD204B MegaCore Function Link initialization Sequences 1.7. Editing and Recompiling the Reference Design 1.8. Document Revision History
1.1. JESD204B MegaCore Function Reference Design x
1.1.1. SYSREF Generator 1.1.2. In-System Sources and Probes (ISSP) 1.1.3. Qsys System 1.1.4. File Directory and Content 1.1.5. Reference Design Initialization Sequence
1.3. Hardware Setup x
1.3.1. FPGA Pin Assignments 1.3.2. Status LED
1. AN 696: Using the JESD204B MegaCore Function in Arria V Devices

1.3.1. FPGA Pin Assignments

The table below lists the top level signals with its corresponding FPGA pin assignments on the Arria V GT FPGA Development Kit.
Table 6.  FPGA 2 Pin Assignments
Top Level Signal Name FPGA 2 Pin Number I/O Standard Direction
device_clk AB9 1.5-V PCML Input
device_clk_n AB8 1.5-V PCML Input
clkintopb_p0 C34 LVDS Input
clkintopb_p0_n D34 LVDS Input
rx_dev_sync_n AD25 2.5-V Output
sysref_out AC24 2.5-V Output
mosi AD24 2.5-V Output
sclk AH27 2.5-V Output
ss_n[0] AG27 2.5-V Output
rx_serial_data[0] U1 1.5-V PCML Input
rx_serial_data_n[0] U2 1.5-V PCML Input
rx_serial_data[1] R1 1.5-V PCML Input
rx_serial_data_n[1] R2 1.5-V PCML Input
Level Two Title