AN 696: Using the JESD204B MegaCore Function in Arria V Devices

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ID 683843
Date 5/11/2015
Public
Document Table of Contents
Document Table of Contents x
1. AN 696: Using the JESD204B MegaCore Function in Arria V Devices
1. AN 696: Using the JESD204B MegaCore Function in Arria V Devices x
1.1. JESD204B MegaCore Function Reference Design 1.2. Hardware and Software Requirements 1.3. Hardware Setup 1.4. Using the Reference Design 1.5. Using the System Console Tool to Execute Commands 1.6. JESD204B MegaCore Function Link initialization Sequences 1.7. Editing and Recompiling the Reference Design 1.8. Document Revision History
1.1. JESD204B MegaCore Function Reference Design x
1.1.1. SYSREF Generator 1.1.2. In-System Sources and Probes (ISSP) 1.1.3. Qsys System 1.1.4. File Directory and Content 1.1.5. Reference Design Initialization Sequence
1.3. Hardware Setup x
1.3.1. FPGA Pin Assignments 1.3.2. Status LED
1. AN 696: Using the JESD204B MegaCore Function in Arria V Devices

1.1.5. Reference Design Initialization Sequence

The following list describes the initialization sequence of the reference design:
  1. Read the MIF content from the FPGA ROM.
  2. Configure AD9517 clock generator.
  3. Configure ADC #2.
  4. Deassert the Avalon-MM reset after the transceiver is out of reset.
  5. Deassert the link and frame reset.
  6. Link layer state machine goes through code group synchronization (CGS), initial lane synchronization (ILAS), and user data phase.
  7. Upon successfully entering the user data phase, the PRBS checker is enabled.
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