AN 696: Using the JESD204B MegaCore Function in Arria V Devices

ID 683843
Date 5/11/2015

1.1.5. Reference Design Initialization Sequence

The following list describes the initialization sequence of the reference design:
  1. Read the MIF content from the FPGA ROM.
  2. Configure AD9517 clock generator.
  3. Configure ADC #2.
  4. Deassert the Avalon-MM reset after the transceiver is out of reset.
  5. Deassert the link and frame reset.
  6. Link layer state machine goes through code group synchronization (CGS), initial lane synchronization (ILAS), and user data phase.
  7. Upon successfully entering the user data phase, the PRBS checker is enabled.