AN 696: Using the JESD204B MegaCore Function in Arria V Devices

ID 683843
Date 5/11/2015
Public

1.3. Hardware Setup

You need to set up the development board before running the reference design.
Hardware Setup
  • The AD9250 module derives power from the FMC connector on the development board.
  • The AD9250 module supplies the device clock to FPGA 2.
  • For subclass 1 mode, the FPGA generates SYSREF for the JESD204B MegaCore function as well as the AD9250 module.


To set up the board connections, perform the following steps:

  1. Install the ADI AD9250 daughter card module to the FMC port (J9) on the development board as shown in figure.
  2. Connect the mini-USB cable to the mini USB connector (J7) on development board.
  3. Connect the power adapter shipped with the development board to the power supply jack (J6).
  4. Turn on the power.
    You are now ready to download the .sof file and program the FPGA device on the development board.

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