AN 696: Using the JESD204B MegaCore Function in Arria V Devices

ID 683843
Date 5/11/2015
Public

1. AN 696: Using the JESD204B MegaCore Function in Arria V Devices

The JESD204B standard provides a serial data link interface between converters and FPGAs. The JESD204B MegaCore function intellectual property (IP) for Altera® FPGAs allows you to transmit and receive data on the FPGA fabric interface by utilizing the Avalon-Streaming (Avalon-ST) source and sink interfaces, with unidirectional flow of data. The JESD204B MegaCore function has been hardware-tested with a number of selected JESD204B-compliant ADC (analog-to-digital converter) device.

This reference design highlights the performance and interoperability of the JESD204B MegaCore function. The design uses an Arria® V GT FPGA Development Kit as well as the Analog Devices Inc. (ADI) AD9250 converter daughter card (evaluation module) connected to the development board.

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