Networking Interface for Open Programmable Acceleration Engine: Intel FPGA Programmable Acceleration Card D5005
2.3. Clock Architecture
This section describes the clocking architecture of the Native PHY IP core.
All four channels on the TX parallel data interface are clocked by f2a_tx_parallel_clk_x2 clock, per QSFP28 interface. Each one of the four channels on the RX parallel data interface is clocked by its own corresponding f2a_rx_clkout[n] clock, per QSFP28 interface.
On both the QSFP28 ports, tx_clkout[n] interfaces of the Native PHY IP core have no connection (NC) because the TX FIFO is in Phase Compensation mode and the f2a_tx_parallel_clk_x2 clock is used to drive the tx_coreclkin[n] interfaces.
On the QSFP28 Port-0, rx_coreclkin[n] interfaces of the Native PHY IP core are connected to rx_clkout[n] interfaces because the RX FIFO is in Phase Compensation mode.
On the QSFP28 Port-1, rx_coreclkin[n] interfaces of the Native PHY IP core are connected to ground because the RX FIFO is in Register mode.
| Clock Name | Frequency in MHz |
|---|---|
| refclk644 | 644.53125 |
| rx_cdr_refclk | 644.53125 |
| tx_serial_clk | 5156.25 |
| f2a_tx_parallel_clk_x1 | 161.1328125 |
| f2a_tx_parallel_clk_x2 | 322.265625 |
| tx_clkout[n] | 322.265625 |
| tx_coreclkin[n] | 322.265625 |
| rx_clkout[n] | 322.265625 |
| rx_coreclkin[n] | 322.265625 |
- rx_clkout[n]
- f2a_tx_parallel_clk_x1
- f2a_tx_parallel_clk_x2
Clock Relationship
- The refclk644, external reference clocks , come from different sources for each QSFP28 network port. Therefore, the relationship between any given clock on network port 0 is asynchronous to any given clock on network port 1.
- The f2a_tx_parallel_clk_x1 and f2a_tx_parallel_clk_x2 are phase synchronous for a given QSFP28 network port.
- The rx_clkout[n] clocks are recovered by the Clock and Data Recovery (CDR) unit in the receiver of each channel. All the rx_clkout[n] clocks are asynchronous to one another.