Networking Interface for Open Programmable Acceleration Engine: Intel FPGA Programmable Acceleration Card D5005

ID 683830
Date 11/04/2019

1. About this Document

Updated for:
Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs 2.0.1
This document describes how to integrate the network port feature into an Accelerator Functional Unit (AFU) and provision it from the host using the Open Programmable Acceleration Engine (OPAE) driver and tools. This document provides information about:
  • Partial Reconfiguration High Speed Serial Interface (HSSI)
  • Intel® Stratix® 10 Native PHY IP core parameters
  • Tuning analog settings