Networking Interface for Open Programmable Acceleration Engine: Intel FPGA Programmable Acceleration Card D5005
3.4. Connecting the PCS to the HSSI Interface
In 32-bit PCS-Direct mode, the interface between the PCS and HSSI PHY maps as following:
| TX Port Function | TX Port | RX Port Function | RX Port |
|---|---|---|---|
| Configuration-32, PMA Width-32, FPGA Fabric width-32 | |||
| data[31:0] | tx_parallel_data[31:0] | data[31:0] | rx_parallel_data[31:0] |
| tx_fifo_wr_en | tx_parallel_data[79] | rx_prbs_err | rx_parallel_data[35] |
| rx_prbs_done | rx_parallel_data[36] | ||
| rx_data_valid | rx_parallel_data[79] | ||
Figure 8. Connecting the PCS to the HSSI Interface
This figure illustrates how to connect a 10GbE PCS to the HSSI PHY using the PR HSSI Interface.