Networking Interface for Open Programmable Acceleration Engine: Intel FPGA Programmable Acceleration Card D5005

ID 683830
Date 11/04/2019

3.2. Data Interface and Signals

The HSSI unified data interface conforms to the Intel® Stratix® 10 FPGA Transceiver Native PHY IP core configured in 32-bit PCS-Direct mode. It consists of generic parallel data and encoding control interfaces for transmit and receive that are mapped to specific signaling behavior as outlined in the Intel® Stratix® 10 L- and H-Tile Transceiver PHY User Guide. The unified data interface also includes flow control ports to manage passing data to and from the HSSI PHY interface.

The table below provides a cross reference from the hssi:raw_pr unified data interface signals to the Intel® Stratix® 10 FPGA Transceiver Native PHY IP core with enhanced PCS signal set. The HSSI PHY IP is configured in Configuration-32, PMA width-32, FPGA Fabric width-32. The TX Core FIFO is configured in Phase Compensation mode. The RX Core FIFO QSFP0 is configured in Phase Compensation mode and RX Core FIFO QSFP1 is configured in Register mode. The Simplified Data Interface is disabled. The Double-Rate Transfer is disabled. For detailed information on these signals, refer to the Intel Stratix 10 L- and H-Tile Transceiver PHY User Guide.

Table 6.  Data Signals
Port Name Width Direction Clock Domain Native PHY IP Port Name Reference
Transmit and Receive Data and Encoding Control Ports
a2f_tx_parallel_data 4*80 Input f2a_tx_parallel_clk_x2 tx_parallel_data PCS-Core Interface Ports: PCS-Direct
f2a_rx_parallel_data 4*80 Output f2a_rx_clkout[n] rx_parallel_data
Flow Control Ports
f2a_tx_fifo_empty 4 Output Reserved
f2a_tx_fifo_full 4 Output Reserved
f2a_tx_fifo_pempty 4 Output Reserved
f2a_tx_fifo_pfull 4 Output Reserved
a2f_rx_bitslip 4 Input Reserved
f2a_rx_fifo_empty 4 Output Reserved
f2a_rx_fifo_full 4 Output Reserved
f2a_rx_fifo_pempty 4 Output Reserved
f2a_rx_fifo_pfull 4 Output Reserved
a2f_rx_fifo_rd_en 4 Input Reserved

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